Just something I didn't make clear in the above comment: I expect that Hardware-description-language-to-layout pipelines will improve a lot in the upcoming year

Just something I didn't make clear in the above comment: I expect that Hardware-description-language-to-layout pipelines will improve a lot in the upcoming years, so if a process becomes viable for open hardware, projects that were developed on an FPGA (here is a wi-fi chip, for instance: https://github.com/open-sdr/openwifi https://github.com/open-sdr/openwifi) might be transferable with a lot less effort than doing everything from scratch. I would also like to point out that these tools will likely help us juice up a bit more performance from the existing processes, but we aren't really likely to see a lot more of Moore's scaling, going forward. So the door is open to new processes, that may or may not be open hardware-friendly. And current, top-end processes might also become cheaper over time. While I doubt a lot of new foundries will catch up with the end of Moore's scale, it might actually become easier to get there, while disruptive technologies get some time to play catch-up. Together with innovative synthesis tools.