5 ms·
What's a way to implement this in practice? Does this article imply that if 1 core was writing the value of a variable (without any locking) and other cores wer
by brickbrd 6y ago
What's a way to implement this in practice? Does this article imply that if 1 core was writing the value of a variable (without any locking) and other cores were simply reading the value of that variable without any locking, it will just work correctly due to underlying CPU cache coherency protocols?