Am I correct in understanding that this paper describes a 'neuromorphic device structure', measures a few instances of it, and then plugs a theoretical model of

Am I correct in understanding that this paper describes a 'neuromorphic device structure', measures a few instances of it, and then plugs a theoretical model of this structure into a simulation? So figure 2A-F are measured on a single device, and figure 2G-I are just simulations based on a model derived from 2A-F and scaled up in silico to large networks? In that case, nothing more than single devices were fabricated, but results reported as a hypothesized neural network... and also if I'm understanding this right, the device is basically a resistor whose resistance can be changed using a series of voltage pulses. This leaves a lot of devilish system implementation details as an exercise to the reader; a system level comparison of this to existing ReRAM (resistive RAM) implementations of DNN accelerators would be enlightening.