I have a couple of articles on my website about my experiences with (previous versions of) Clash if anyone wants some examples. I used Clash in a processor desi

I have a couple of articles on my website about my experiences with (previous versions of) Clash if anyone wants some examples. I used Clash in a processor design class and it was amazing. We had some "competitions" between the various CPUs in the class (e.g. performance and correctness given some ISA spec) and I was able to create one of the top few CPUs with only a small fraction of the effort of my classmates using a "traditional" HDL like VHDL or Verilog. Slides from a clash talk I gave in probably 2016: https://yager.io/talks/CLaSH.pdf https://yager.io/talks/CLaSH.pdf Simple non-pipelined CPU (I've been meaning to release part 2 for years but never got around to it): https://yager.io/CPU/CPU1.html https://yager.io/CPU/CPU1.html SKI calculus processor on an FPGA: https://yager.io/HaSKI/HaSKI.html https://yager.io/HaSKI/HaSKI.html A superscalar out-of-order processor I built for a CPU design class at UT Austin: https://github.com/wyager/Lambda17 https://github.com/wyager/Lambda17 (Take a look at Hardware.hs to see some of the cool parametric stuff you can do.) Like I said, these are all with old versions of Clash - it's changed in the last few years, but I haven't done any HDL projects recently.