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Verilog and VHDL have something akin to this form of imperative meta-programming. (See Verilog's "generate" and "genvar" keywords for example). But there is n
by jhallenworld 6y ago
Verilog and VHDL have something akin to this form of imperative meta-programming. (See Verilog's "generate" and "genvar" keywords for example).
But there is no iterating over or building members of an interface (the closest thing SystemVerilog has to a user defined type).