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RISC-V is basically a nonstarter. It has a lot of ridiculously goofy decisions in its ISA, it doesn't seem like competent CPU nor compiler engineers were ever i

RISC-V is basically a nonstarter. It has a lot of ridiculously goofy decisions in its ISA, it doesn't seem like competent CPU nor compiler engineers were ever in the loop for its design, and the number one benefit seems to be the licensing terms that make it super easy to extend or even replace 90% of the ISA while still calling it "RISC-V".

monocasa 7y ago
Can you enumerate some of these goofy decisions?
- Jasper_ 7y ago
  Sure. The most notable one I can think of is that integer multiplication is not in core. It's an extension. Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity, and used with the same frequency. And for one example for how goofy of an idea that is, ARM has never included integer division in its core ISA. Then there's the whole JALR mess, which I don't know how to describe it other than "tech debt". Basically, they tried to simplify different kinds of jumps and returns into a single extension, by allowing any register to be used for the source and destination addresses. But for branch prediction reasons, and prefetching, you really do want to have a single link register, so the spec says "please don't use anything other than x1 as the link register, or you might not get proper performance". There's a lot more that I can go into.
  - monocasa 7y ago
    > The most notable one I can think of is that integer multiplication is not in core. It's an extension. Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. Those use cases work just fine with the shifts and adds trick you can do for multiply by constant. Honestly I was always baffled that ARMv6-M required a multiplier. Seemed to be the closest thing to an albatross over it's head, so much so that there were those M0's with an iterative, 32 cycle latency, bit serial multiplier. > Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity, and used with the same frequency. And for one example for how goofy of an idea that is, ARM has never included integer division in its core ISA. ARMv7-M (the closest ISA to Rv32-EM) requires integer divide. > Then there's the whole JALR mess, which I don't know how to describe it other than "tech debt". Basically, they tried to simplify different kinds of jumps and returns into a single extension, by allowing any register to be used for the return address. But for branch prediction reasons, you really do want to have a single link register, so the spec says "please don't use anything other than x1 as the link register, or you might not get proper performance". I don't really see this as a problem. For instance it neatly encodes unconditional jump without link as a jump with link to x0. Reminds me of some of the cute ways to encodes jumps from SH without being quite as ascetic. > There's a lot more that I can go into. Please do. Like totally unironically. I obviously have a pretty high opinion of RISC-V, but I appreciate someone who helps keep my biases in check.
  - magicalhippo 7y ago
    > Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity I was under the impression that cores with only a hardware multiplier could emulate the division instruction. From the ISA specification[1]: "RV32I can emulate almost any other ISA extension". [1]: https://riscv.org/specifications/isa-spec-pdf/ https://riscv.org/specifications/isa-spec-pdf/ (Chapter 2, RV32I Base Integer Instruction Set,)
  - magicalhippo 7y ago
    > "please don't use anything other than x1 as the link register, or you might not get proper performance" What's wrong with supporting a slow path? The alternative is to say x1 is always used, in which case you don't get the flexible, but more costly, alternative register variant, no?
  - saagarjha 6y ago
    > Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. I think those transform to an integer multiplication…like never? They're almost always an offset to a base pointer that's incremented as you go through the loop…
  - p0llard 6y ago
    > The most notable one I can think of is that integer multiplication is not in core. And? Base RISC-V is meant to be as simple as possible; if you're designing an ultra-low power microcontroller you probably don't want a hardware multiplier, and you shouldn't be forced to have one. The "G" general purpose set of extensions is what you need for an application processor. Something like RV64GC would be what most compiler writers would be targetting. > telling me that the spec authors think that multiplication and division are of the same circuit complexity Given the profiles of the spec authors I highly doubt this is the case; the number of modern cores which support hardware multiplication but not division is very small. > Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. For a loop you'll probably try to avoid as much multiplication as possible by transforming the induction variable to make it amenable to strength reduction.
m463 7y ago
Your words sound like the description of linux around 2000. or the arguments against an operating system in C instead of assembler years before that. The licensing terms are what make risc-v interesting and the technical arguments won't stand the test of time.

monocasa 7y ago

Can you enumerate some of these goofy decisions?

Jasper_ 7y ago
Sure. The most notable one I can think of is that integer multiplication is not in core. It's an extension. Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity, and used with the same frequency. And for one example for how goofy of an idea that is, ARM has never included integer division in its core ISA. Then there's the whole JALR mess, which I don't know how to describe it other than "tech debt". Basically, they tried to simplify different kinds of jumps and returns into a single extension, by allowing any register to be used for the source and destination addresses. But for branch prediction reasons, and prefetching, you really do want to have a single link register, so the spec says "please don't use anything other than x1 as the link register, or you might not get proper performance". There's a lot more that I can go into.
- monocasa 7y ago
  > The most notable one I can think of is that integer multiplication is not in core. It's an extension. Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. Those use cases work just fine with the shifts and adds trick you can do for multiply by constant. Honestly I was always baffled that ARMv6-M required a multiplier. Seemed to be the closest thing to an albatross over it's head, so much so that there were those M0's with an iterative, 32 cycle latency, bit serial multiplier. > Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity, and used with the same frequency. And for one example for how goofy of an idea that is, ARM has never included integer division in its core ISA. ARMv7-M (the closest ISA to Rv32-EM) requires integer divide. > Then there's the whole JALR mess, which I don't know how to describe it other than "tech debt". Basically, they tried to simplify different kinds of jumps and returns into a single extension, by allowing any register to be used for the return address. But for branch prediction reasons, you really do want to have a single link register, so the spec says "please don't use anything other than x1 as the link register, or you might not get proper performance". I don't really see this as a problem. For instance it neatly encodes unconditional jump without link as a jump with link to x0. Reminds me of some of the cute ways to encodes jumps from SH without being quite as ascetic. > There's a lot more that I can go into. Please do. Like totally unironically. I obviously have a pretty high opinion of RISC-V, but I appreciate someone who helps keep my biases in check.
- magicalhippo 7y ago
  > Even more baffling, is that the same extension that adds integer multiplication, also requires integer division, telling me that the spec authors think that multiplication and division are of the same circuit complexity I was under the impression that cores with only a hardware multiplier could emulate the division instruction. From the ISA specification[1]: "RV32I can emulate almost any other ISA extension". [1]: https://riscv.org/specifications/isa-spec-pdf/ https://riscv.org/specifications/isa-spec-pdf/ (Chapter 2, RV32I Base Integer Instruction Set,)
- magicalhippo 7y ago
  > "please don't use anything other than x1 as the link register, or you might not get proper performance" What's wrong with supporting a slow path? The alternative is to say x1 is always used, in which case you don't get the flexible, but more costly, alternative register variant, no?
- saagarjha 6y ago
  > Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. I think those transform to an integer multiplication…like never? They're almost always an offset to a base pointer that's incremented as you go through the loop…
- p0llard 6y ago
  > The most notable one I can think of is that integer multiplication is not in core. And? Base RISC-V is meant to be as simple as possible; if you're designing an ultra-low power microcontroller you probably don't want a hardware multiplier, and you shouldn't be forced to have one. The "G" general purpose set of extensions is what you need for an application processor. Something like RV64GC would be what most compiler writers would be targetting. > telling me that the spec authors think that multiplication and division are of the same circuit complexity Given the profiles of the spec authors I highly doubt this is the case; the number of modern cores which support hardware multiplication but not division is very small. > Anybody that's written a compiler or even stared at assembly would tell you how prevalent integer multiplication is, for any sort of loop or pointer addressing. For a loop you'll probably try to avoid as much multiplication as possible by transforming the induction variable to make it amenable to strength reduction.

m463 7y ago

Your words sound like the description of linux around 2000. or the arguments against an operating system in C instead of assembler years before that. The licensing terms are what make risc-v interesting and the technical arguments won't stand the test of time.