Since it's what I'm typing this on, let's look at Skylake. Multiply: Latency 3, Throughput 1 Shift: Latency 1, Throughput 2 If the ALU contained an early out

Since it's what I'm typing this on, let's look at Skylake. Multiply: Latency 3, Throughput 1 Shift: Latency 1, Throughput 2 If the ALU contained an early out or fast path for simpler multiplies, the latency would read 1-3. You can verify this by looking at div, which does early out and has a latency of 35-88. Any compiler that doesn't swap a multiply to a shift when it can is negligent. https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf