The "asrs" mnemonics are the same, but the opcodes use different addressing modes. The 4th instruction in the longer sequence is a register-to-register move, w

The "asrs" mnemonics are the same, but the opcodes use different addressing modes. The 4th instruction in the longer sequence is a register-to-register move, which might be a simple register rename. It's not obvious to me that the shorter sequence is necessarily faster than the longer one. OK, the "adds" is probably slower, and introduces a register dependency. But the whole exercise here is to test and see, not trust that some simple operation performs like how it looks. Indeed, if you discount the "bx lr" (that's just the return, right?), the 1-instruction version takes 3ns, and the 4-instruction version takes 4ns. Clearly, 4 times as many instructions is not taking anywhere near 4 times as long to execute.