"Verilog and VHDL are unquestionably terrible languages (they weren't even intended to be HDLs, that use case came later)" They were intended to be HDLs (for s

"Verilog and VHDL are unquestionably terrible languages (they weren't even intended to be HDLs, that use case came later)" They were intended to be HDLs (for simulation of hardware), but they were never intended to be automatically translated into gates/schematics (i.e., synthesized)