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The word leakage used in the context of the article refers to a single transistor, not neighboring devices. See this Wiki article. What is commonly called "lea

The word leakage used in the context of the article refers to a single transistor, not neighboring devices. See this Wiki article. What is commonly called "leakage" is more formally called "subthreshold conduction". The two n+ areas of the FET are the source and drain. In that particular picture a conducting channel between those two would be formed when Vg is positive. The problem is that, for a variety of reasons, when the devices are that small it is difficult to keep current from flowing between drain and source even if Vg is zero. https://en.wikipedia.org/wiki/Subthreshold_conduction https://en.wikipedia.org/wiki/Subthreshold_conduction In a "traditional" FET, as shown above, the channel is formed in the region below the gate. If you look at the "FinFET’s Features" illustration in the IEEE article the orange area is where the channel can be formed. It is no longer simply "below" the gate, but instead exists as a three dimensional structure. This gives the gate voltage more control of the current flowing between source and drain.

bogomipz 6y ago
Thank you for the wonderful explanation. This is really helpful. Cheers.
brennanpeterson 6y ago
A reasonably good physical picture is to imagine the transistor as a hose. The gate is a valve, and basically works by smushing the channel closed. In standard planar designs, the hose is smushed from the too, and eventually, you cannot close off that flow. A finfet let's you smush that channel.closed from three sides. And a nanowire or sheet let's you close it from all sides. You can reasonably ask: why not make it really small and make sure it closes. The reason is that you need current to drive the computation process. So anyway, you balance these factors at each node, which is what BSIM lets you do.
- bogomipz 6y ago
  >"And a nanowire or sheet let's you close it from all sides." Interesting so is this why we see the research into carbon nano-tubes or is that something else? >"So anyway, you balance these factors at each node, which is what BSIM lets you do." What is BSIM here?

bogomipz 6y ago

Thank you for the wonderful explanation. This is really helpful. Cheers.

brennanpeterson 6y ago

A reasonably good physical picture is to imagine the transistor as a hose. The gate is a valve, and basically works by smushing the channel closed. In standard planar designs, the hose is smushed from the too, and eventually, you cannot close off that flow. A finfet let's you smush that channel.closed from three sides. And a nanowire or sheet let's you close it from all sides. You can reasonably ask: why not make it really small and make sure it closes. The reason is that you need current to drive the computation process. So anyway, you balance these factors at each node, which is what BSIM lets you do.

bogomipz 6y ago
>"And a nanowire or sheet let's you close it from all sides." Interesting so is this why we see the research into carbon nano-tubes or is that something else? >"So anyway, you balance these factors at each node, which is what BSIM lets you do." What is BSIM here?