I've only got partial insight into this, so maybe someone else can fill in gaps. Power consumption in a digital chip traditionally happens many ways: dynamic p

I've only got partial insight into this, so maybe someone else can fill in gaps. Power consumption in a digital chip traditionally happens many ways: dynamic power is the energy consumed moving charge around to actually flip a signal at a transistor. For the same clock speed, it goes down as feature size goes down, because gate capacitance is smaller so less charge needs to be deposited/removed on the gate to raise/lower its voltage by a given amount (also increases with clock speed for the same feature size, because more charges/discharges per unit time). Static power is current draining through (often, always?, parasitic) resistive paths, and needs to be either be provided all the time, or requires a minimum clock frequency so that the voltage is still detectable when you need to. This actually drives the minimum refresh rate on DRAM. The big change, what I understood as a surprise when it happened (I was an undergrad EE while this hit the industry), was when insulator structures got thin enough that electrons were actually quantum tunneling "through" them. Now you've got a new parasitic path for charge to drain away, and on top of that it changes the performance of your transistor. At the time, and I want to say this was the 45nm process node, but it could've been 90nm, gates oxides (insulators) were ~5 atoms thick. Unfortunately, I didn't really stick with this part of EE, so I'm not sure what to say about the thinner channels.