"smallest type" doesn't go far enough for HDL languages - consider a 4-bit counter in verilog reg [3:0]r; r = 4'hf; r = r+1; if (r == 0) .... if r is really

"smallest type" doesn't go far enough for HDL languages - consider a 4-bit counter in verilog reg [3:0]r; r = 4'hf; r = r+1; if (r == 0) .... if r is really 8 bits r+1 will have a non-0 value .... However all the LLVM people may be saying here is that they're providing the minimal support for arbitrary size math and expect language implementers to generate the masking where required (ie that r+1 above is really (r+1)&4'hf ) I'll note that for Verilog in particular the standard Verilog C-level APIs for accessing data imply that integers are not stored contiguously, instead they're stored in 32-bit chunks with a min size of 32-bits for 1 to 32-bit values - a 33-64 bit value will be stored in 2 non-contiguous 32-bit words ('packed' values are different from this). To be useful any back end support needs to be able to understand stuff stored this way.