5 ms·

How the Father of FinFETs Helped Save Moore’s Law

166 points by matt_d 7y ago

lawrenceyan 7y ago
I've seen Professor Hu on campus a few times, and it was a really cool experience being able to talk to him in person. I only wish I could have taken a course with him, but he doesn't do as much teaching unfortunately these days.
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0xff00ffee 7y ago
I had no idea he started work on FinFETs in the 90's. That's crazy because I worked on them at Intel during the first process (which was an absolute beast to bring up), and I just assumed they were a new tech. Funny that often the people on the cutting edge don't get a chance to appreciate the history.
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- bogomipz 7y ago
  >"That's crazy because I worked on them at Intel during the first process (which was an absolute beast to bring up)" Could you elaborate on this? Do you mean bringing the the process node/fab online? More so of a beast than other other nodes? Cheers.
  - 0xff00ffee 7y ago
    No, I can't elaborate because I wasn't on the process team, I just used their parameters. I watched the agony on faces of friends on-call 24/7 who owned the yields... that was close enough for me. :) Yes, I meant bringing up the process node. Yes, more so than other nodes, but for context I only go back to p854, so earlier might have been worse.
    - eternauta3k 7y ago
      Were you in charge of the models? If so, any resources you could share? Conferences, books, whatever.
      - 0xff00ffee 7y ago
        Oh hellz no! I was just a consumer. Lots and lots of people use the process files for all kinds of modeling (hundreds of models). And every time a new one comes out we all spend a month switching over to it... and another month explaining to our bosses why everything got worse! The people in charge of the model need to be very smart, very diplomatic, and very thick-skinned because every release they have literally hundreds of managers and project leads screaming at them.
        eternauta3k 7y ago
        I know what you mean. Designers are more worried about simulation results not changing, than they are about matching reality better :)
cooper12 7y ago
The fascinating part of this article is the path it took for FinFETs to go from a theoretical all the way to fruition. You have things like him hearing about a DARPA grant last-minute from a surfing buddy. He also was working in different areas throughout his career. Great quote: > His career soon took a detour because semiconductors, he recalls, just seemed too easy. He switched to researching optical circuits, did his Ph.D. thesis on integrated optics...
- eternauta3k 7y ago
  > him hearing about a DARPA grant last-minute from a surfing buddy I was very disappointed to go the article and find that Hu does not in fact surf: > Hu had heard about the DARPA funding from a fellow Berkeley faculty member, Jeffrey Bokor, who, in turn, had heard about it while windsurfing with a DARPA program director
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tanilama 7y ago
So he made the biggest achievement in his life at the age of 48, and waited another another 15 years for it to become reality. Never too late.
- eternauta3k 7y ago
  I imagine most academics never see the impact of their work.
bogomipz 7y ago
What an amazing career. I had a couple of questions. The articles states: >"The main problem was power. As features grew smaller, current that leaked through when a transistor was in its “off” state became a bigger issue. This leakage is so great that it increased—or even dominated—a chip’s power consumption." How exactly does residual current start to dominate? Does this mean that current starts to leak into neighboring transistors and inadvertently turn them on? >"Hu saw the fundamental problem as quite clear—making the channel very thin to prevent electrons from sneaking past the gate?" I would have thought that making the channels thinner make current flow through them easier. Why does making them thinner prevent current leakage exactly?
- patrickyeon 7y ago
  I've only got partial insight into this, so maybe someone else can fill in gaps. Power consumption in a digital chip traditionally happens many ways: dynamic power is the energy consumed moving charge around to actually flip a signal at a transistor. For the same clock speed, it goes down as feature size goes down, because gate capacitance is smaller so less charge needs to be deposited/removed on the gate to raise/lower its voltage by a given amount (also increases with clock speed for the same feature size, because more charges/discharges per unit time). Static power is current draining through (often, always?, parasitic) resistive paths, and needs to be either be provided all the time, or requires a minimum clock frequency so that the voltage is still detectable when you need to. This actually drives the minimum refresh rate on DRAM. The big change, what I understood as a surprise when it happened (I was an undergrad EE while this hit the industry), was when insulator structures got thin enough that electrons were actually quantum tunneling "through" them. Now you've got a new parasitic path for charge to drain away, and on top of that it changes the performance of your transistor. At the time, and I want to say this was the 45nm process node, but it could've been 90nm, gates oxides (insulators) were ~5 atoms thick. Unfortunately, I didn't really stick with this part of EE, so I'm not sure what to say about the thinner channels.
- ramshanker 7y ago
  >How exactly does residual current start to dominate? I guess sum total of leakage current in all the OFF transistor coming up more than the sum total of all the ON transistor current. Assuming at any point of time, more than 50% transistors are OFF, there are so many OP codes in x86/64, only few of them could be active at a time.
tails4e 7y ago
This guy is seriously impressive. As the article mentions the BSIM models developed by him at Berkeley are the corner stone of all transistor simulations today, modelling thousands of subtle effects - an impressive feat, not only to build the accurate picture of a transistor and its environment (the effects on the transistor function from being near others, etc) but also to do it in a way that allows modern EDA tools to simulation 100k+ at once in a reasonable amount of time. It's also impressive he made impacts in so many different aspects, transistors, solar cells, optical, etc. Well deserved award.
- eternauta3k 7y ago
  If anyone is interested in what these transistor models are like, there's an excellent online course by Yannis Tsividis: https://www.coursera.org/learn/mosfet https://www.coursera.org/learn/mosfet
DeathArrow 7y ago
Unfortunately, it's not Moore's law that make the chips run faster, but Denard's scaling and that seems to no longer work. [0][1] [0] http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07.pdf http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07... [1] https://cartesianproduct.wordpress.com/2013/04/15/the-end-of-dennard-scaling/ https://cartesianproduct.wordpress.com/2013/04/15/the-end-of...
Causality1 7y ago
We're really good at scaling and getting more performance per watt but it seems like our performance per transistor is essentially stagnant. Is this an area where we could focus development as silicon shrinking dies?
- eternauta3k 7y ago
  Scaling is improving single-transistor performance, specifically the switching time / transition frequency.

166 points by matt_d 7y ago

I've seen Professor Hu on campus a few times, and it was a really cool experience being able to talk to him in person. I only wish I could have taken a course with him, but he doesn't do as much teaching unfortunately these days.

deleted 7y ago
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0762361114 7y ago

Create Account

0762361114 7y ago

13000$

0xff00ffee 7y ago

I had no idea he started work on FinFETs in the 90's. That's crazy because I worked on them at Intel during the first process (which was an absolute beast to bring up), and I just assumed they were a new tech. Funny that often the people on the cutting edge don't get a chance to appreciate the history.

deleted 7y ago
[deleted]
bogomipz 7y ago
>"That's crazy because I worked on them at Intel during the first process (which was an absolute beast to bring up)" Could you elaborate on this? Do you mean bringing the the process node/fab online? More so of a beast than other other nodes? Cheers.
- 0xff00ffee 7y ago
  No, I can't elaborate because I wasn't on the process team, I just used their parameters. I watched the agony on faces of friends on-call 24/7 who owned the yields... that was close enough for me. :) Yes, I meant bringing up the process node. Yes, more so than other nodes, but for context I only go back to p854, so earlier might have been worse.
  - eternauta3k 7y ago
    Were you in charge of the models? If so, any resources you could share? Conferences, books, whatever.
    - 0xff00ffee 7y ago
      Oh hellz no! I was just a consumer. Lots and lots of people use the process files for all kinds of modeling (hundreds of models). And every time a new one comes out we all spend a month switching over to it... and another month explaining to our bosses why everything got worse! The people in charge of the model need to be very smart, very diplomatic, and very thick-skinned because every release they have literally hundreds of managers and project leads screaming at them.
      - eternauta3k 7y ago
        I know what you mean. Designers are more worried about simulation results not changing, than they are about matching reality better :)

cooper12 7y ago

The fascinating part of this article is the path it took for FinFETs to go from a theoretical all the way to fruition. You have things like him hearing about a DARPA grant last-minute from a surfing buddy. He also was working in different areas throughout his career. Great quote: > His career soon took a detour because semiconductors, he recalls, just seemed too easy. He switched to researching optical circuits, did his Ph.D. thesis on integrated optics...

eternauta3k 7y ago
> him hearing about a DARPA grant last-minute from a surfing buddy I was very disappointed to go the article and find that Hu does not in fact surf: > Hu had heard about the DARPA funding from a fellow Berkeley faculty member, Jeffrey Bokor, who, in turn, had heard about it while windsurfing with a DARPA program director

deleted 7y ago

[deleted]

tanilama 7y ago

So he made the biggest achievement in his life at the age of 48, and waited another another 15 years for it to become reality. Never too late.

eternauta3k 7y ago
I imagine most academics never see the impact of their work.

bogomipz 7y ago

What an amazing career. I had a couple of questions. The articles states: >"The main problem was power. As features grew smaller, current that leaked through when a transistor was in its “off” state became a bigger issue. This leakage is so great that it increased—or even dominated—a chip’s power consumption." How exactly does residual current start to dominate? Does this mean that current starts to leak into neighboring transistors and inadvertently turn them on? >"Hu saw the fundamental problem as quite clear—making the channel very thin to prevent electrons from sneaking past the gate?" I would have thought that making the channels thinner make current flow through them easier. Why does making them thinner prevent current leakage exactly?

patrickyeon 7y ago
I've only got partial insight into this, so maybe someone else can fill in gaps. Power consumption in a digital chip traditionally happens many ways: dynamic power is the energy consumed moving charge around to actually flip a signal at a transistor. For the same clock speed, it goes down as feature size goes down, because gate capacitance is smaller so less charge needs to be deposited/removed on the gate to raise/lower its voltage by a given amount (also increases with clock speed for the same feature size, because more charges/discharges per unit time). Static power is current draining through (often, always?, parasitic) resistive paths, and needs to be either be provided all the time, or requires a minimum clock frequency so that the voltage is still detectable when you need to. This actually drives the minimum refresh rate on DRAM. The big change, what I understood as a surprise when it happened (I was an undergrad EE while this hit the industry), was when insulator structures got thin enough that electrons were actually quantum tunneling "through" them. Now you've got a new parasitic path for charge to drain away, and on top of that it changes the performance of your transistor. At the time, and I want to say this was the 45nm process node, but it could've been 90nm, gates oxides (insulators) were ~5 atoms thick. Unfortunately, I didn't really stick with this part of EE, so I'm not sure what to say about the thinner channels.
ramshanker 7y ago
>How exactly does residual current start to dominate? I guess sum total of leakage current in all the OFF transistor coming up more than the sum total of all the ON transistor current. Assuming at any point of time, more than 50% transistors are OFF, there are so many OP codes in x86/64, only few of them could be active at a time.

tails4e 7y ago

This guy is seriously impressive. As the article mentions the BSIM models developed by him at Berkeley are the corner stone of all transistor simulations today, modelling thousands of subtle effects - an impressive feat, not only to build the accurate picture of a transistor and its environment (the effects on the transistor function from being near others, etc) but also to do it in a way that allows modern EDA tools to simulation 100k+ at once in a reasonable amount of time. It's also impressive he made impacts in so many different aspects, transistors, solar cells, optical, etc. Well deserved award.

eternauta3k 7y ago
If anyone is interested in what these transistor models are like, there's an excellent online course by Yannis Tsividis: https://www.coursera.org/learn/mosfet https://www.coursera.org/learn/mosfet

DeathArrow 7y ago

Unfortunately, it's not Moore's law that make the chips run faster, but Denard's scaling and that seems to no longer work. [0][1] [0] http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07.pdf http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07... [1] https://cartesianproduct.wordpress.com/2013/04/15/the-end-of-dennard-scaling/ https://cartesianproduct.wordpress.com/2013/04/15/the-end-of...

Causality1 7y ago

We're really good at scaling and getting more performance per watt but it seems like our performance per transistor is essentially stagnant. Is this an area where we could focus development as silicon shrinking dies?

eternauta3k 7y ago
Scaling is improving single-transistor performance, specifically the switching time / transition frequency.