Much of my time is spent writing Mentor Catapult HLS for ASIC designs these days. Every HLS vendor or language has their own, incompatible arbitrary bitwidth i

Much of my time is spent writing Mentor Catapult HLS for ASIC designs these days. Every HLS vendor or language has their own, incompatible arbitrary bitwidth integer type at present. SystemC sc_int is different from Xilinx Vivado ap_int is different from Mentor Catapult ac_int is different from whatever Intel had for their Altera FPGAs. It's a real mess. I'm hoping this is another small step to slowly move the industry into a more unified representation, or at least if LLVM support for this at the type level could enable faster simulation of designs on CPU by improving the CPU code that is emitted. What probably matters most for HLS though are the operations which are performed on the types (static or dynamic bit slicing, etc).