Not to mention that the first statement is simply false... The final result is a bitstream that determines which LUTs (lookup tables) and BRAM (memory/block RA

Not to mention that the first statement is simply false... The final result is a bitstream that determines which LUTs (lookup tables) and BRAM (memory/block RAM) to use on the chip, and how they should be connected/routed. The FPGA fabric itself is made of transistors, but your C/C++ (HLS) or HDL code is not directly controlling these transistors. This is what makes FPGAs so flexible relative to ASICs.