3 ms·
> Reading from memory was slow, it took 4 cycles, which normally would be filled with NOPs by the C compiler (1 load instruction, 3 NOPs). So, I'd use assembly
by pcwalton 7y ago
> Reading from memory was slow, it took 4 cycles, which normally would be filled with NOPs by the C compiler (1 load instruction, 3 NOPs). So, I'd use assembly instead of C and try to fill those NOPs with other actual operations that didn't need the memory being requested, essentially doing hand-crafted concurrency.
This isn't usual for the MIPS ISA, is it? MIPS has branch delay slots but not memory delay slots, per my understanding. (Of course if there's a data dependency on a pending load the CPU still has to stall.)
- louthy 7y agoThe R3000 suffered from the need for load delay slots too, unfortunately. I may have forgotten all the exact details though. I am genuinely in awe of people who seem to retain the details of this stuff 10 - 20 years later, my brain certainly doesn't work like that!