movaps, movups (granted, those perform similarly on the latest intel chips) Alignment can make caching simpler: an aligned load/store will never cross a cache

movaps, movups (granted, those perform similarly on the latest intel chips) Alignment can make caching simpler: an aligned load/store will never cross a cache boundary. So some architectures will have faster aligned access. This is the case for RISC-V. It's not so much that unaligned access is being punished there, as aligned access being optimized