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The problem with disabling this optimisation is that it will produce garbage code for basically every architecture. Code which does unaligned accesses are notic
by cyphar 7y ago
The problem with disabling this optimisation is that it will produce garbage code for basically every architecture. Code which does unaligned accesses are noticeably slow compared to aligned accesses -- this is why there are separate instructions and intrinsics for aligned and unaligned addresses on most architectures. That way you don't pay the penalty of unaligned accesses all the time. But if you try to use the aligned instructions on unaligned pointers you will get all sorts of fun errors.
And note that this slowdown would have to apply to every pointer operation in your program because GCC can't know whether a pointer is aligned at compile-time. I'm sure many more people would complain about significant performance slowdowns in a GCC update than about unaligned memory accesses being something you need to do with great care in C.
- pron 7y ago> And note that this slowdown would have to apply to every pointer operation in your program because No, because I think that on x86 the instructions are the same for aligned and unaligned up to, and including, 64 bits (quadword). The only slowdown that would occur is due to missed compiler optimizations, and the author proposed disabling them as an option.
- vardump 7y agoYes, up to 64 bits. They're different for x86 SIMD (128 bits and up, SSE & AVX). For example vmovapd (requires alignment) vs vmovupd (can be unaligned).
- nkurz 7y ago> The problem with disabling this optimisation is that it will produce garbage code for basically every architecture. I'm pretty sure this this is not true for modern x64, which is one of the most common desktop architectures: https://lemire.me/blog/2012/05/31/data-alignment-for-speed-myth-or-reality/ https://lemire.me/blog/2012/05/31/data-alignment-for-speed-m... Which current architectures are you thinking of? Do you have comparable benchmarks showing the slowdown?
- loeg 7y agoExcepting misalignment that causes a variable to straddle a cache line, modern x86 is generally extremely tolerant of misalignment, performance-wise (for GPR-sized operations). Newer x86 is even pretty performant in the face of misaligned vector-sized accesses.