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Few seem to know x86 can generate misaligned access exception. Enabling EFLAGS Alignment Check (bit 18) flag causes an exception on any misaligned access, if th
by vardump 7y ago
Few seem to know x86 can generate misaligned access exception. Enabling EFLAGS Alignment Check (bit 18) flag causes an exception on any misaligned access, if the kernel has enabled this feature by setting CR0 register Alignment Mask (bit 18).
- SomeoneFromCA 7y agoYou do not need to enable anything. SSE instructions require aligned access, and will crash if used with wrong alignment, irrespective of the flag.
- vardump 7y agoI was talking about scalar 16, 32 and 64 bit alignments. You're confusing that with SSE alignment requirements. Besides, SSE has unaligned load & store as well.
- magicalhippo 7y agoI noticed this when I discovered the NVIDIA OpenGL driver used SSE without thinking. Nothing in the OpenGL specs says the buffers passed to it (think it was glBufferData) has to be 16byte aligned, but with NVIDIA it would crash with an alignment exception if they were not. The memory allocater in the language I used, Delphi, only used 4 byte alignment (32bit). They might have fixed this, this was well over a decade ago.