3 ms·

-fno-strict-aliasing: https://stackoverflow.com/questions/98650/what-is-the-strict-aliasing-rule https://stackoverflow.com/questions/98650/what-is-the-strict...

by __s 7y ago

-fno-strict-aliasing: https://stackoverflow.com/questions/98650/what-is-the-strict-aliasing-rule https://stackoverflow.com/questions/98650/what-is-the-strict... Torvalds rant: https://www.yodaiken.com/2018/06/07/torvalds-on-aliasing https://www.yodaiken.com/2018/06/07/torvalds-on-aliasing edit: I misread the parent as wondering about a compiler flag

eqvinox 7y ago
Irrelevant to the post, even without strict aliasing the compiler will assume pointers/objects are properly aligned.
- hedora 7y ago
  Do you have an example where the compiler generates bad code that doesn’t involve misaligned aliases? Many programs rely on misaligned access, and features like pragma packed do too. I doubt they’ll be able to break all of that legacy code.
  - eqvinox 7y ago
    > Many programs rely on misaligned access, and features like pragma packed do too. I doubt they’ll be able to break all of that legacy code. It's already broken. You're just not seeing it on x86. (Not sure how tolerant ARM is.) I work in network software engineering, i.e. PowerPC used to be a common architecture. Those never accepted misaligned pointers (albeit you could of course trap the misalignment exception and emulate the access, or print a backtrace to identify the location.) Really this is a problem caused by the "common case" (x86) being permissive in what it accepts, creating fallout further down the line if you ever need the code to run on something less permissive. [Edit: actually, oops, it's not PowerPC; those are relatively permissive too. Pretty sure DEC Alpha and m68k are restrictive.]
    - loeg 7y ago
      I think newer aarch64 allows misaligned access to regular memory.
- Gibbon1 7y ago
  Yeah but alignment is a really really stupid thing to enforce on modern hardware. It makes absolutely no sense at all. All you are doing is increasing your cache pressure and limiting memory bandwidth.
  - __s 7y ago
    movaps, movups (granted, those perform similarly on the latest intel chips) Alignment can make caching simpler: an aligned load/store will never cross a cache boundary. So some architectures will have faster aligned access. This is the case for RISC-V. It's not so much that unaligned access is being punished there, as aligned access being optimized
    - Gibbon1 7y ago
      Yeah but your cache and memory layout are swiss cheese.

by __s 7y ago

eqvinox 7y ago

Irrelevant to the post, even without strict aliasing the compiler will assume pointers/objects are properly aligned.

hedora 7y ago
Do you have an example where the compiler generates bad code that doesn’t involve misaligned aliases? Many programs rely on misaligned access, and features like pragma packed do too. I doubt they’ll be able to break all of that legacy code.
- eqvinox 7y ago
  > Many programs rely on misaligned access, and features like pragma packed do too. I doubt they’ll be able to break all of that legacy code. It's already broken. You're just not seeing it on x86. (Not sure how tolerant ARM is.) I work in network software engineering, i.e. PowerPC used to be a common architecture. Those never accepted misaligned pointers (albeit you could of course trap the misalignment exception and emulate the access, or print a backtrace to identify the location.) Really this is a problem caused by the "common case" (x86) being permissive in what it accepts, creating fallout further down the line if you ever need the code to run on something less permissive. [Edit: actually, oops, it's not PowerPC; those are relatively permissive too. Pretty sure DEC Alpha and m68k are restrictive.]
  - loeg 7y ago
    I think newer aarch64 allows misaligned access to regular memory.
Gibbon1 7y ago
Yeah but alignment is a really really stupid thing to enforce on modern hardware. It makes absolutely no sense at all. All you are doing is increasing your cache pressure and limiting memory bandwidth.
- __s 7y ago
  movaps, movups (granted, those perform similarly on the latest intel chips) Alignment can make caching simpler: an aligned load/store will never cross a cache boundary. So some architectures will have faster aligned access. This is the case for RISC-V. It's not so much that unaligned access is being punished there, as aligned access being optimized
  - Gibbon1 7y ago
    Yeah but your cache and memory layout are swiss cheese.