4 ms·

> by 4,5x on AVX2 I would expect a much smaller gap as AVX2 is also available through intrinsics on C ?!

by tromp 7y ago

pjmlp 7y ago
CPU intrinsics are just another way of doing inline Assembly.
- dhhwrongagain 7y ago
  False or vacuously true
- throwaway_pdp09 7y ago
  IANA C/C++/ASM expert, but one thing I've been thinking of would greatly benefit from type-punning (overlaying 2 kinds of data and interpreting one as the other) because it can use a 64-bit register to parallelise 4 ops at once where speed really, really matters. That's trivial in ASM I believe, but don't know how well it's possible in C/C++, if at all.
  - saagarjha 7y ago
    Type punning in general would be somewhat difficult to do here in a way that vectorized but was still defined by the standard. You’d need to put a branch with undefined behavior in it when alignment wasn’t satisfied, then do a memcpy into a vector type, and hope that the compiler understands what you’re doing and doesn’t deoptimize it.
  - pjmlp 7y ago
    I fail to see why not just use a __m64 variable and do the conversion. https://software.intel.com/sites/landingpage/IntrinsicsGuide/ https://software.intel.com/sites/landingpage/IntrinsicsGuide... You can also try to make a union whose one field is a __m64, but beware not to trigger UB conditions.
jbk 7y ago
That is still writing asm. You need to write it, the compiler cannot do it by itself.
Someone 7y ago
When using Clang org CC (possibly other compilers, too), you don’t need to use intrinsics. These compilers have some support for vector types (https://clang.llvm.org/docs/LanguageExtensions.html#vectors-and-extended-vectors https://clang.llvm.org/docs/LanguageExtensions.html#vectors-..., https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html) One can, for example, write: typedef int v4si __attribute__ ((vector_size (16))); v4si a, b, c; […] b += 3; // add 3 to each of b’s elements c = a + b; // pairwise addition Using this gives up some control over assembly; it doesn’t guarantee vector instructions get used, but it makes it easier for the compiler to generate them. Also, I’m fairly sure there are vector instructions not covered by this extension.

> by 4,5x on AVX2 I would expect a much smaller gap as AVX2 is also available through intrinsics on C ?!

by tromp 7y ago

> by 4,5x on AVX2 I would expect a much smaller gap as AVX2 is also available through intrinsics on C ?!

pjmlp 7y ago

CPU intrinsics are just another way of doing inline Assembly.

dhhwrongagain 7y ago
False or vacuously true
throwaway_pdp09 7y ago
IANA C/C++/ASM expert, but one thing I've been thinking of would greatly benefit from type-punning (overlaying 2 kinds of data and interpreting one as the other) because it can use a 64-bit register to parallelise 4 ops at once where speed really, really matters. That's trivial in ASM I believe, but don't know how well it's possible in C/C++, if at all.
- saagarjha 7y ago
  Type punning in general would be somewhat difficult to do here in a way that vectorized but was still defined by the standard. You’d need to put a branch with undefined behavior in it when alignment wasn’t satisfied, then do a memcpy into a vector type, and hope that the compiler understands what you’re doing and doesn’t deoptimize it.
- pjmlp 7y ago
  I fail to see why not just use a __m64 variable and do the conversion. https://software.intel.com/sites/landingpage/IntrinsicsGuide/ https://software.intel.com/sites/landingpage/IntrinsicsGuide... You can also try to make a union whose one field is a __m64, but beware not to trigger UB conditions.

jbk 7y ago

That is still writing asm. You need to write it, the compiler cannot do it by itself.

Someone 7y ago

When using Clang org CC (possibly other compilers, too), you don’t need to use intrinsics. These compilers have some support for vector types (https://clang.llvm.org/docs/LanguageExtensions.html#vectors-and-extended-vectors https://clang.llvm.org/docs/LanguageExtensions.html#vectors-..., https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html https://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html) One can, for example, write: typedef int v4si __attribute__ ((vector_size (16))); v4si a, b, c; […] b += 3; // add 3 to each of b’s elements c = a + b; // pairwise addition Using this gives up some control over assembly; it doesn’t guarantee vector instructions get used, but it makes it easier for the compiler to generate them. Also, I’m fairly sure there are vector instructions not covered by this extension.