4 ms·
Interesting that no one to my knowledge has built an architecture where sram is ‘memory’ such that it would be transparent to C code but no slower dram is used.
by mcot2 6y ago
Interesting that no one to my knowledge has built an architecture where sram is ‘memory’ such that it would be transparent to C code but no slower dram is used. 32MB is more than my 1998 computer had.
- jnwatson 6y agoMany embedded systems have a block of SRAM directly addressable.