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remember that with ryzen that is split up between chunks of cores, so its not entirely flexible. that gets better with the upcoming generation though, its more
by gameswithgo 7y ago
remember that with ryzen that is split up between chunks of cores, so its not entirely flexible.
that gets better with the upcoming generation though, its more unified.
- admax88q 7y agoThe L3 is split per core? I thought it was only typically L1 cache that was per core, with L2 and L3 being shared across the entire die.
- gameswithgo 7y agonot per core, but per ccx. a ccx is a group of cores. if you need something that isn't in your ccx's chunk of l3 cache you have to hop through the memory controller and pay a latency penalty.
- brobinson 7y agoCan you disable cores to get more cache per (actually running) core?
- wmf 7y agoYes. That is what AMD is doing with these chips; e.g. the 32-core version has 64 cores with half disabled and you can disable more if you want.
- akiselev 7y agoI thought the chiplets were binned before getting placed onto the carrier silicon, so they wouldn't need to do the core fusing that Intel does?
- wmf 7y agoThere's no carrier silicon and I'm not sure what distinction you're making between binning and fusing. The only way to get 256 MB of cache is to also have 64 cores, the only way to get 192 MB is to have 48, etc.
- brobinson 7y agoIs this possible on first gen Ryzen? I have the 1950x, and I don't see any option to deactivate cores in my BIOS.
- wmf 7y agoYou can do it in Linux https://www.thegeekdiary.com/how-to-enable-disable-cpus-limiting-cpu-count-in-centos-rhel/ https://www.thegeekdiary.com/how-to-enable-disable-cpus-limi... or Windows https://solidlystated.com/software/how-to-disable-a-cpu-core/ https://solidlystated.com/software/how-to-disable-a-cpu-core...
- brobinson 7y agoWow, I did not realize this was done through `msconfig` on Windows. Thank you very much for the links.