4 ms·

We made our original CPU&ISA emulator over TFHE. https://github.com/virtualsecureplatform/kvsp https://github.com/virtualsecureplatform/kvsp Because we use chi

We made our original CPU&ISA emulator over TFHE. https://github.com/virtualsecureplatform/kvsp https://github.com/virtualsecureplatform/kvsp Because we use chisel to write CPU and we also made LLVM backend for our original CPU, your idea is not so difficult although it may be very slow. Our original CPU is about 4K gates. The most difficult point is building memory because it is most slow part. We used TFHE's LHE mode for it and this is one of the novel points of our work. (We didn't know about Shape CPU but it seems to be similar to FURISC, which is published and using libScarab.https://eprint.iacr.org/2015/699 https://eprint.iacr.org/2015/699)

nindanaoto 6y ago
Our original CPU, CAHP-emerald is 5 stage pipeline, super-scalar processor. Pipelining improved performance well. https://github.com/virtualsecureplatform/cahp-emerald https://github.com/virtualsecureplatform/cahp-emerald
mmastrac 6y ago
Interesting. FURISC looks like it cribbed a lot of ideas off ShapeCPU without referencing prior art. I find it hard to believe someone would be working on a libScarab-based CPU without seeing ShapeCPU as well. Encrypted termination conditions were definitely in that implementation. The memory mux too.
- nindanaoto 6y ago
  I'm also doubting that but before I knew Shape CPU, I believed because FURISC seems to be based on HEROIC, which is claimed to be the first processor emulation over homomorphic encryption. https://past.date-conference.com/proceedings-archive/PAPERS/2014/DATE14/PDFFILES/09.3_4.PDF https://past.date-conference.com/proceedings-archive/PAPERS/... I think FURISC is more like HEROIC than ShapeCPU. By the way, I feel sad for there is no publication of ShapeCPU. I guess that this is one of the causes of FURISC paper is lacking reference for ShapeCPU.
  - mmastrac 6y ago
    It looks like ShapeCPU originated around 2012 but only made it into posters, not papers. It's kind of a shame because I spent quite some time reproducing their work to confirm that it was viable, then building on top of it with HideCPU. Lots of prior art in that implementation!

nindanaoto 6y ago

Our original CPU, CAHP-emerald is 5 stage pipeline, super-scalar processor. Pipelining improved performance well. https://github.com/virtualsecureplatform/cahp-emerald https://github.com/virtualsecureplatform/cahp-emerald

mmastrac 6y ago

Interesting. FURISC looks like it cribbed a lot of ideas off ShapeCPU without referencing prior art. I find it hard to believe someone would be working on a libScarab-based CPU without seeing ShapeCPU as well. Encrypted termination conditions were definitely in that implementation. The memory mux too.

nindanaoto 6y ago
I'm also doubting that but before I knew Shape CPU, I believed because FURISC seems to be based on HEROIC, which is claimed to be the first processor emulation over homomorphic encryption. https://past.date-conference.com/proceedings-archive/PAPERS/2014/DATE14/PDFFILES/09.3_4.PDF https://past.date-conference.com/proceedings-archive/PAPERS/... I think FURISC is more like HEROIC than ShapeCPU. By the way, I feel sad for there is no publication of ShapeCPU. I guess that this is one of the causes of FURISC paper is lacking reference for ShapeCPU.
- mmastrac 6y ago
  It looks like ShapeCPU originated around 2012 but only made it into posters, not papers. It's kind of a shame because I spent quite some time reproducing their work to confirm that it was viable, then building on top of it with HideCPU. Lots of prior art in that implementation!