This happened to me. We were seeing a USB issue between a Marvell SoC we purchased and a Qualcomm SoC. The more I tried to understand this issue, the deeper th

This happened to me. We were seeing a USB issue between a Marvell SoC we purchased and a Qualcomm SoC. The more I tried to understand this issue, the deeper the rabbit hole went until we were in the weeds of the XHCI controller looking at scatter/gather operations, etc. Eventually we bought a USB protocol analyzer that seemed to indicate that the actual host controller had a bug. We contacted the Marvell, who in turn contacted the vendor of the USB core (Synopsys). They bisected USB cores with an FPGA until they found a day which had a breaking change. Unfortunately, it appears Synopsys didn't use version control with their source verilog a few years ago (they just had archived daily builds), so while they could say "yep, looks like something that changed on 13 Jan 2015 broke it" they didn't know what change that was. However, before it could be resolved the company I was working for went bankrupt and so I never did get closure on the issue. I sunk many, many months into understanding that issue over the course of several years only to give up because it was near impossible to understand enough to come up with a workaround (and because the company went bankrupt).