Well if you've just run your verification on FPGA like that chances are your silicon will fall over on first boot because you've totally missed a whole bunch of

Well if you've just run your verification on FPGA like that chances are your silicon will fall over on first boot because you've totally missed a whole bunch of corners cases that only occur on the real memory system. Yes you can attempt to emulate these in FPGA but that's one of the reasons verification is not as easy as it seems. > Start with the simplest possible in-order core so that you get it working very easily, and then evolve to your desired end-state with a series of small commits You can't just trivially evolve a simple design into something more complex, much in the same way when Linux does a new major release they haven't started with some stripped down basic *nix and worked their way up from there.