Because GPIO for communication protocols is what is termed "bit banging", normally for high speed communication stuff you have a dedicated ASIC that handles all

Because GPIO for communication protocols is what is termed "bit banging", normally for high speed communication stuff you have a dedicated ASIC that handles all the low level signaling itself and presents a high level (possibly DMA) interface to the CPU. With bit banging/gpio you are using the CPU itself to write/read the raw binary signal of the GPIO, usually with no buffering. This involves tight loops and polling and is slow because the CPU must marshal and construct all signaling (including timing!) in a synchronous way, bit by bit, rather than just dumping a block of data into memory somewhere and having a high level ASIC deal with it (or reading said block). A good analogy might be writing your friend a long note and then having him read (The high level interface) it vs phoning your friend and sharing the note, one letter at a time.(the low level bit banging interface), which do you suppose would be faster, and less demanding of your attention?