3 ms·

Transmission time isn’t really the main issue, it’s more about the work required to get a memory request through the levels of the hierarchy to DRAM and back. P

Transmission time isn’t really the main issue, it’s more about the work required to get a memory request through the levels of the hierarchy to DRAM and back. Probing each level of cache, propagating through the miss queues, translation (maybe with TLB miss), waiting for the DRAM controller, etc.

RaoulP 7y ago
Interesting - if that's the case I would imagine it make sense for some systems to feature an architecture which skips the idea of multilevel cache entirely and has only RAM connected over a photonic bus. No probing, no cache misses.
adwn 7y ago
What? That doesn't make sense. If cache probing would be the cause for DRAM accesses being slow, we wouldn't need caches. We would just access DRAM directly! It's the other way around: DRAM accesses are slow, that's why we need caches. > translation (maybe with TLB miss) In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. Successful TLB lookups are extremely fast! And you can't skip the TLB, even if you don't have any data caches.
- MrBuddyCasino 7y ago
  > In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. So to see if a memory location is contained in a cache line, a TLB lookup is needed to first get the physical address? I wouldn't have expected this, can you expand on why this is the case?
  - pwildani 7y ago
    If you use virtual addresses to index your caches, you have to clear them all on every process context switch. With physical addresses, you just have to clear your TLB cache.
  - dooglius 7y ago
    See Linus Torvalds' thesis, section 4.3.3 "The case against virtual data caches": https://www.cs.helsinki.fi/u/kutvonen/index_files/linus.pdf https://www.cs.helsinki.fi/u/kutvonen/index_files/linus.pdf
  - adwn 7y ago
    Two reasons: 1) a virtual address might refer to different physical addresses (see pwildani's comment), and 2) a physical address can be mapped to different virtual addresses – a virtually addresses cache has to keep track of that somehow, otherwise the cache will become incoherent.
- Sheppy96 7y ago
  I wasn’t suggesting probing caches is the main cost, I only wanted to describe that there is a long journey to DRAM in current architectures of which signal propagation is such a small part. You are totally right that if you can make the resultant communication speed faster you could theoretically do away with caches. However this approach wouldn’t solve that problem on its own. Also forget not that cache is expensive and DRAM is cheap! Yes I’m aware that caches can be physically addressed and you could reorder the sequence I described. No you can’t skip the TLB, but a hit will be faster since you don’t have to perform translation.

RaoulP 7y ago

Interesting - if that's the case I would imagine it make sense for some systems to feature an architecture which skips the idea of multilevel cache entirely and has only RAM connected over a photonic bus. No probing, no cache misses.

adwn 7y ago

What? That doesn't make sense. If cache probing would be the cause for DRAM accesses being slow, we wouldn't need caches. We would just access DRAM directly! It's the other way around: DRAM accesses are slow, that's why we need caches. > translation (maybe with TLB miss) In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. Successful TLB lookups are extremely fast! And you can't skip the TLB, even if you don't have any data caches.

MrBuddyCasino 7y ago
> In most architectures, the caches are physically addressed, so TLB lookups occur before even L1 cache access. So to see if a memory location is contained in a cache line, a TLB lookup is needed to first get the physical address? I wouldn't have expected this, can you expand on why this is the case?
- pwildani 7y ago
  If you use virtual addresses to index your caches, you have to clear them all on every process context switch. With physical addresses, you just have to clear your TLB cache.
- dooglius 7y ago
  See Linus Torvalds' thesis, section 4.3.3 "The case against virtual data caches": https://www.cs.helsinki.fi/u/kutvonen/index_files/linus.pdf https://www.cs.helsinki.fi/u/kutvonen/index_files/linus.pdf
- adwn 7y ago
  Two reasons: 1) a virtual address might refer to different physical addresses (see pwildani's comment), and 2) a physical address can be mapped to different virtual addresses – a virtually addresses cache has to keep track of that somehow, otherwise the cache will become incoherent.
Sheppy96 7y ago
I wasn’t suggesting probing caches is the main cost, I only wanted to describe that there is a long journey to DRAM in current architectures of which signal propagation is such a small part. You are totally right that if you can make the resultant communication speed faster you could theoretically do away with caches. However this approach wouldn’t solve that problem on its own. Also forget not that cache is expensive and DRAM is cheap! Yes I’m aware that caches can be physically addressed and you could reorder the sequence I described. No you can’t skip the TLB, but a hit will be faster since you don’t have to perform translation.