3 ms·
> So reducing a dozen instructions to a single instruction doesn't necessarily mean that the single instruction is going to be faster. Are you saying dozen sca
by vardump 7y ago
> So reducing a dozen instructions to a single instruction doesn't necessarily mean that the single instruction is going to be faster.
Are you saying dozen scalar instructions can be faster than one vector instruction? That's wrong 100% of time on modern CPUs.
- nickysielicki 7y agoYeah, I think there exists a case where this is possible. Let me play around with it this weekend and I'll comment here if I find anything.
- vardump 7y agoI know it can happen on some older ARM designs, microcontrollers and weird DSP-like etc. chips. But I can't think of any case on modern x86 chips at least. Some low-performance ARMv7/8 designs can split NEON SIMD instructions into multiple clock cycles, but I think even then NEON is going to perform better.
- nickysielicki 7y agoI started digging into it but I don't have an intel machine with linux easily available and that's a prerequisite for looking at microop performance. I think you win.
- vardump 7y agoI don't need to win, I just want the truth to win. In other words, I'd consider it a win if I, you or anyone else learns something new. SIMD is highly optimized at this point, with sustainable two instructions per clock throughput. It's hard to imagine scalar getting anywhere near even at 4 inst/clk rates.
- jcranmer 7y agoOne corner case that exists is that using AVX instructions imposes a frequency limit, although this isn't the case for SSE instructions. There exist some vector instructions that are going to be slower than a non-equivalent sequence of scalar instructions: VPGATHER is going to be an easy such case. However, I doubt there are going to be any cases where a vector instruction will take fewer clock cycles than its equivalent scalarized instructions. There are some where it might be equivalent--a vector of 2 elements performing an operation that can be issued twice a cycle is an easy example--but I can't think of any where it would be worse. If that were the case, then you should just implement the operation in hardware by scalarizing the uops (and some instructions appear to be so implemented--e.g., gather/scatter).
- vardump 7y agoVPGATHER is actually significantly faster than scalar loads at least on Skylake, possibly on some earlier CPUs as well (Broadwell?). On Haswell where it was first introduced... yeah, not very fast, like you mentioned.