Implementing the Beta processor (32-bit RISC processor loosely based on the DEC Alpha) for 6.004 [0] was one of the most fun projects I've done. We wrote every

Implementing the Beta processor (32-bit RISC processor loosely based on the DEC Alpha) for 6.004 [0] was one of the most fun projects I've done. We wrote everything at the netlist level (or at least I'm told it's roughly equivalent to SPICE's netlists) rather than VHDL or Verilog, with some simple component libraries (mostly 2-,3-,and 4-input MUXes/DEMUXes) and a register file implementation provided by the instructors. These days, I would hope they'd use a simplified ISA based on either RISC-V or something as close to 64-bit ARM as they could legally get away with. [0] https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2009/tools/ https://ocw.mit.edu/courses/electrical-engineering-and-compu...