The question isn't whether it's going to be better than Itanium. Of course it will (assuming it ever becomes a real product, of course), since it's using a seve

The question isn't whether it's going to be better than Itanium. Of course it will (assuming it ever becomes a real product, of course), since it's using a several generations better process. Itanium was never particularly impressive compared to its (roughly) contemporary competitors on the (roughly) same process, why would Tachyon be any better? You say that tradeoffs change as a function of the process. E.g. wires becoming ever more expensive compared to transistors. Is that enough to tilt the playing field in favour of VLIW? I can see VLIW having an advantage here if the VLIW instruction bundle lines up 1:1 with the hardware pipelines (less routing inside the chip), and the workload is static so you can use profile guided optimization to work around the lack of dynamic scheduling (OoO). However, once you try to create a VLIW ISA that maps to several generations and/or high/low end implementations you lose that 1:1 mapping, and for general purpose code compile time scheduling isn't particularly good. As Intel found out.