The Mill architecture has some neat ideas here where you can issue a load in cycle 10 but specify it to arrive in cycle, say, 80 so the cpu can be busy for anot

The Mill architecture has some neat ideas here where you can issue a load in cycle 10 but specify it to arrive in cycle, say, 80 so the cpu can be busy for another 70 cycles whether or not the loaded value is in the cache or not.