4 ms·
Is there a EILI5 on why Intel borked 10nm and why others apparently didn't?
by scottlocklin 7y ago
Is there a EILI5 on why Intel borked 10nm and why others apparently didn't?
- chx 7y agoELI5? Not really. 1. The metal pitch targeted (36nm) requires Self-Aligned Quad Patterning (SAQP) apparently is very very hard to do without EUV. TSMC is doing 40nm metal pitch and Samsung does 36nm BUT both of them are using EUV. 2. Cobalt https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/ https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-inte... 3. COAG https://www.reddit.com/r/AMD_Stock/comments/dk2pw7/why_it_is_so_difficult_for_intel_to_catch_up_the/f4ml1k4 https://www.reddit.com/r/AMD_Stock/comments/dk2pw7/why_it_is...
- Symmetry 7y agoI think the ELI5 is "Intel tried to do some things that were cleverer than they could actually do and messed up."
- scottlocklin 7y agoI remember them developing an EUV lithography rig at the ALS 11 bend magnet in the 90s... guess it never worked out. Looking at the website: dude's still there! Thanks for the explanation; close enough to ELI5