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Maybe you have a different definition in mind than I do? I'm using microcode to mean sequences of micro-ops. Wikipedia [0] seems to agree, "the microcode is a l

Maybe you have a different definition in mind than I do? I'm using microcode to mean sequences of micro-ops. Wikipedia [0] seems to agree, "the microcode is a layer of hardware-level instructions that implement higher-level machine code instructions or internal state machine sequencing in many digital processing elements". My understanding is that with a couple exceptions (IIRC mov and zeroing xor are treated specially as part of register renaming) all assembly instructions get translated into microcode (i.e. a sequence of micro-ops). [0] https://en.wikipedia.org/wiki/Microcode https://en.wikipedia.org/wiki/Microcode

Jasper_ 7y ago
I don't have the patience to go fix Wikipedia, but microcode is a patching system (it's what "processor microcode updates" means). Most of the time, that's adjusting chicken bits and other flags. Instructions can be implemented in microcode, but they are really, really slow so it's typically done for security reasons or to emulate some new features that don't require fast performance. Micro-ops are part of the micro-architecture of the processor, and are in hardware. They are not patchable and are not software.
- vardump 7y ago
  Microcode on x86? Don't forget to also greet our friends such as RDTSCP, CPUID, RDMSR, POPCNT (on some models) etc. Also remember to check ENTER, BOUND, etc. out in the museum vitrine. But yeah, microcoded instructions are relatively rarely executed.
  - Jasper_ 7y ago
    I can't find any evidence that RDTSCP is microcoded. That would defeat the whole purpose of a high-performance counter. Any source?
    - vardump 7y ago
      I can't find any primary source, but I'm pretty sure about it.
    - PeCaN 7y ago
      Agner Fog's instruction tables list it as issuing ~23 fused uops (a bit more or fewer depending on generation) and a throughput of 1 per ~32 cycles. That seems like it could be microcoded.
- throwaway_pdp09 7y ago
  I don't think wikipedia is broken, so plz don't fix. The definition of microcode matches my understanding. I've never heard it used as a patching system per se, ever.
  - Jasper_ 7y ago
    What do you think those "processor microcode updates" are, then? They don't have anything to do with micro-ops, or really have any influence over the core micro-architecture. It would be way too slow to make that programmable. People have this common misconception that the programmable micro-code is what your CPU is actually executing, and x86 somehow translates into instructions for it, and this was really just because of a conflation of the terms "micro-code" and "micro-op". Admittedly, Intel isn't the best at this term either. They have several places in the Architecture Manuals where they refer to the "micro-code synthesizer" when they mean "micro-op synthesizer"; this really has nothing to do with the micro-code ROM.
    - throwaway_pdp09 7y ago
      They're for updating the microcode. That is tangential to their use AIUI, but useful. Also AIUI the microcode controls the issuing of the micro-ops. > It would be way too slow to make that programmable Then what is the "processor microcode updates" updating? I think this may just be a terminology mixup. Dunno if this helps, FYI from https://stackoverflow.com/questions/17395557/observing-stale-instruction-fetching-on-x86-with-self-modifying-code/18388700#18388700 https://stackoverflow.com/questions/17395557/observing-stale... ...and I can't copy/paste it. In the above link, look for 'embarrassing' by Krazy Glew.
- Twirrim 7y ago
  An example of Instructions being implemented in Microcode is AMD's implementation of PDEP and PEXT on the Zen and Zen2 chips, leading to shockingly bad performance of 289 cycles vs 1 on Intel: https://twitter.com/uops_info/status/1202950247900684290 https://twitter.com/uops_info/status/1202950247900684290 https://github.com/llvm-project/llvm/blob/master/lib/Target/X86/X86ScheduleZnver1.td#L747 https://github.com/llvm-project/llvm/blob/master/lib/Target/...

Jasper_ 7y ago

I don't have the patience to go fix Wikipedia, but microcode is a patching system (it's what "processor microcode updates" means). Most of the time, that's adjusting chicken bits and other flags. Instructions can be implemented in microcode, but they are really, really slow so it's typically done for security reasons or to emulate some new features that don't require fast performance. Micro-ops are part of the micro-architecture of the processor, and are in hardware. They are not patchable and are not software.

vardump 7y ago
Microcode on x86? Don't forget to also greet our friends such as RDTSCP, CPUID, RDMSR, POPCNT (on some models) etc. Also remember to check ENTER, BOUND, etc. out in the museum vitrine. But yeah, microcoded instructions are relatively rarely executed.
- Jasper_ 7y ago
  I can't find any evidence that RDTSCP is microcoded. That would defeat the whole purpose of a high-performance counter. Any source?
  - vardump 7y ago
    I can't find any primary source, but I'm pretty sure about it.
  - PeCaN 7y ago
    Agner Fog's instruction tables list it as issuing ~23 fused uops (a bit more or fewer depending on generation) and a throughput of 1 per ~32 cycles. That seems like it could be microcoded.
throwaway_pdp09 7y ago
I don't think wikipedia is broken, so plz don't fix. The definition of microcode matches my understanding. I've never heard it used as a patching system per se, ever.
- Jasper_ 7y ago
  What do you think those "processor microcode updates" are, then? They don't have anything to do with micro-ops, or really have any influence over the core micro-architecture. It would be way too slow to make that programmable. People have this common misconception that the programmable micro-code is what your CPU is actually executing, and x86 somehow translates into instructions for it, and this was really just because of a conflation of the terms "micro-code" and "micro-op". Admittedly, Intel isn't the best at this term either. They have several places in the Architecture Manuals where they refer to the "micro-code synthesizer" when they mean "micro-op synthesizer"; this really has nothing to do with the micro-code ROM.
  - throwaway_pdp09 7y ago
    They're for updating the microcode. That is tangential to their use AIUI, but useful. Also AIUI the microcode controls the issuing of the micro-ops. > It would be way too slow to make that programmable Then what is the "processor microcode updates" updating? I think this may just be a terminology mixup. Dunno if this helps, FYI from https://stackoverflow.com/questions/17395557/observing-stale-instruction-fetching-on-x86-with-self-modifying-code/18388700#18388700 https://stackoverflow.com/questions/17395557/observing-stale... ...and I can't copy/paste it. In the above link, look for 'embarrassing' by Krazy Glew.
Twirrim 7y ago
An example of Instructions being implemented in Microcode is AMD's implementation of PDEP and PEXT on the Zen and Zen2 chips, leading to shockingly bad performance of 289 cycles vs 1 on Intel: https://twitter.com/uops_info/status/1202950247900684290 https://twitter.com/uops_info/status/1202950247900684290 https://github.com/llvm-project/llvm/blob/master/lib/Target/X86/X86ScheduleZnver1.td#L747 https://github.com/llvm-project/llvm/blob/master/lib/Target/...