4 ms·
This has nothing to do with microcode. It doesn't even have anything to do with microops. Reordering instructions (likely register renaming or load-store forwar
by Jasper_ 7y ago
This has nothing to do with microcode. It doesn't even have anything to do with microops. Reordering instructions (likely register renaming or load-store forwarding here, though the pseudo C code doesn't let me determine) is just part of how the processor retires instructions.
- vardump 7y agoThe example I gave, yes. No assembler code can have anything to do with micro-ops; they're implementation specific. On x86, a lot of instructions are close matches, yet some are removed entirely (say "xor eax, eax") or fused into one micro-op, (like "cmp #123, eax / je <address>"). Future CPUs might even do some data flow analysis to optimize code even further. Say speculative "constant" folding based on runtime profile to remove chunks of code from hot inner loops. Or to replace longer instruction patterns with HW optimized implementation, if that's what it takes to get some extra performance for the next year's model. https://en.wikichip.org/wiki/macro-operation_fusion https://en.wikichip.org/wiki/macro-operation_fusion
- Jasper_ 7y agoRegisters are allocated (and renamed) after instruction decode (e.g. what creates micro-ops), in a separate unit. Micro ops themselves do not have renamed registers. See the diagram here https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf#page=52 https://software.intel.com/sites/default/files/managed/9e/bc...
- vardump 7y agoTrue. I simplified implementation details for clarity.