One of the key points of the paper is about how OpenCL makes it easier to implement things for an FPGA. Using Verilog/VHDL is about an order of magnitude more w

One of the key points of the paper is about how OpenCL makes it easier to implement things for an FPGA. Using Verilog/VHDL is about an order of magnitude more work, which would probably completely disqualify using the FPGA for a project like this.