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From device cross sections and working at both IDMs and suppliers. And reading and visiting IEDM for a decade. You can keepmup with ost on semiwiki: but really,
by brennanpeterson 7y ago
From device cross sections and working at both IDMs and suppliers. And reading and visiting IEDM for a decade. You can keepmup with ost on semiwiki: but really, just work under the assumption that people in the field are not stupid and can do math.
Tensile strains has no litho impact, and counting layers in use was a job I had.
Who spent on 3-5? It got press coverage, but never was part of much logic research. It was a focus for power, laser, and led work.
Tsmc, Intel, applied, asm, and others spent vastly more on r&d than any government or academic work, and it isn't published.
- baybal2 7y agoI'll give you that. I haven't been involved with device and process development since around 2009, when I lost hope getting into process engineering. So, were strained channels used with FinFETs on anything mainstream? I heard the news of number of foundries dropping straining at around the time of first finfets.