I’m almost finished with a RISCV core in verilog targeting FPGAs: https://github.com/thejefflarson/little-cpu https://github.com/thejefflarson/little-cpu I’m

I’m almost finished with a RISCV core in verilog targeting FPGAs: https://github.com/thejefflarson/little-cpu https://github.com/thejefflarson/little-cpu I’m four instructions away from implementing the compressed extensions, and probably next week I’ll tackle the control and status registers. It uses an open source tool chain and is formally verified using riscv-formal. My hope is to eventually be able to compile some rust and get an fpga to blink an led :)