The chip has a CCPI (Cache Coherent Processor Interface) with 24 lanes @ 25Gb/s for 2-socket NUMA interconnect. This technology came from Cavium (who bought th

The chip has a CCPI (Cache Coherent Processor Interface) with 24 lanes @ 25Gb/s for 2-socket NUMA interconnect. This technology came from Cavium (who bought the Raza, then NetLogic, then Broadcom, and very briefly Avago XLS/XLR/XLP/Vulcan designs from Avago before being bought themselves by Marvell). I don't recall it being in their MIPS64-based Octeon II or III designs, and I thought the XLP had some minimal-glue NUMA support, but I can't find anything with a quick search. Minimal info at Wikichip: https://en.wikichip.org/wiki/cavium/ccpi https://en.wikichip.org/wiki/cavium/ccpi