6 ms·

240W, 96 quite beefy ARM cores, I'm not sure about SMT. All that in 1U. The density is becoming mad.

namibj 7y ago
That sounds like a shrink of a single ThunderX2 socket. I'd say, expect two of this in a 1U system, or maybe rather 2 separate 2S boards in a 2U case with shared power/cooling.
adev_ 7y ago
If they continue what they were doing for TX2 [^1] , you might get double socket in 1U. Meaning 192 cores per U. [1]: https://www.gigabyte.com/ARM-Server/R181-T90-rev-100 https://www.gigabyte.com/ARM-Server/R181-T90-rev-100
- deleted 7y ago
  [deleted]
- __d 7y ago
  The chip has a CCPI (Cache Coherent Processor Interface) with 24 lanes @ 25Gb/s for 2-socket NUMA interconnect. This technology came from Cavium (who bought the Raza, then NetLogic, then Broadcom, and very briefly Avago XLS/XLR/XLP/Vulcan designs from Avago before being bought themselves by Marvell). I don't recall it being in their MIPS64-based Octeon II or III designs, and I thought the XLP had some minimal-glue NUMA support, but I can't find anything with a quick search. Minimal info at Wikichip: https://en.wikichip.org/wiki/cavium/ccpi https://en.wikichip.org/wiki/cavium/ccpi
wyldfire 7y ago
> The Triton chip will have eight memory controllers supporting memory running at 3.2 GHz, which is the same number of controllers in the Vulcan chip, which maxxed out at 2.67 GHz memory speeds. That’s a 20 percent increase in memory bandwidth, and the question is how that will balance out against the high core counts in some of the Triton SKUs. 96 cores, seems like it would be tricky to keep them busy with modest memory throughput increases.
- kingosticks 7y ago
  Do they really mean memory running at 3.2GHz? What memory would be running that fast? Isn't this HBM2E and it's 3.2Gbps bandwidth?
  - mastax 7y ago
    DDR4 easily runs at 3200 MHz (DDR) though I don't know if that's common yet for ECC RDIMMS.
    - kingosticks 7y ago
      Doh! yes, thanks, that makes a LOT more sense!
    - deleted 7y ago
      [deleted]
- thedance 7y ago
  That's a comparable configuration to an AMD EPYC "Rome" with 48c/96t and 8 memory controllers.
- mastax 7y ago
  For certain workloads, having 4SMT will keep the cores busy while they're waiting on main memory.
skavi 7y ago
It’s SMT4, so up to 384 threads per socket.
- rbanffy 7y ago
  We'll need to update htop to use the Unicode 2x2 mosaics so we can cram 2 vCores per line and use foreground and background colors cleverly...
- navaati 7y ago
  Geeeeee ! They said in the article that the previous gen chip was, but didn't explicitely confirm for the new one, so I didn't dare to hope. Thanks for the confirmation !
ksec 7y ago
384 Thread or vCPU in a single socket or 768 vCPU per 1U in Dual Socket. That is ~$4K per month revenue for Cloud Vendor. Unfortunately DRAM, NAND and Bandwidth unit cost hasn't drop a bit compared to vCPU unit cost. Along with baseline price of Rent and Electricity which means Cloud Vendors unit cost aren't that much better. I expect this would only come to 10 to 20% price drop.

That sounds like a shrink of a single ThunderX2 socket. I'd say, expect two of this in a 1U system, or maybe rather 2 separate 2S boards in a 2U case with shared power/cooling.

adev_ 7y ago

If they continue what they were doing for TX2 [^1] , you might get double socket in 1U. Meaning 192 cores per U. [1]: https://www.gigabyte.com/ARM-Server/R181-T90-rev-100 https://www.gigabyte.com/ARM-Server/R181-T90-rev-100

deleted 7y ago
[deleted]
__d 7y ago
The chip has a CCPI (Cache Coherent Processor Interface) with 24 lanes @ 25Gb/s for 2-socket NUMA interconnect. This technology came from Cavium (who bought the Raza, then NetLogic, then Broadcom, and very briefly Avago XLS/XLR/XLP/Vulcan designs from Avago before being bought themselves by Marvell). I don't recall it being in their MIPS64-based Octeon II or III designs, and I thought the XLP had some minimal-glue NUMA support, but I can't find anything with a quick search. Minimal info at Wikichip: https://en.wikichip.org/wiki/cavium/ccpi https://en.wikichip.org/wiki/cavium/ccpi

wyldfire 7y ago

> The Triton chip will have eight memory controllers supporting memory running at 3.2 GHz, which is the same number of controllers in the Vulcan chip, which maxxed out at 2.67 GHz memory speeds. That’s a 20 percent increase in memory bandwidth, and the question is how that will balance out against the high core counts in some of the Triton SKUs. 96 cores, seems like it would be tricky to keep them busy with modest memory throughput increases.

kingosticks 7y ago
Do they really mean memory running at 3.2GHz? What memory would be running that fast? Isn't this HBM2E and it's 3.2Gbps bandwidth?
- mastax 7y ago
  DDR4 easily runs at 3200 MHz (DDR) though I don't know if that's common yet for ECC RDIMMS.
  - kingosticks 7y ago
    Doh! yes, thanks, that makes a LOT more sense!
  - deleted 7y ago
    [deleted]
thedance 7y ago
That's a comparable configuration to an AMD EPYC "Rome" with 48c/96t and 8 memory controllers.
mastax 7y ago
For certain workloads, having 4SMT will keep the cores busy while they're waiting on main memory.

skavi 7y ago

It’s SMT4, so up to 384 threads per socket.

rbanffy 7y ago
We'll need to update htop to use the Unicode 2x2 mosaics so we can cram 2 vCores per line and use foreground and background colors cleverly...
navaati 7y ago
Geeeeee ! They said in the article that the previous gen chip was, but didn't explicitely confirm for the new one, so I didn't dare to hope. Thanks for the confirmation !

ksec 7y ago

384 Thread or vCPU in a single socket or 768 vCPU per 1U in Dual Socket. That is ~$4K per month revenue for Cloud Vendor. Unfortunately DRAM, NAND and Bandwidth unit cost hasn't drop a bit compared to vCPU unit cost. Along with baseline price of Rent and Electricity which means Cloud Vendors unit cost aren't that much better. I expect this would only come to 10 to 20% price drop.