It’s nice to see the use of 4-way SMT on Arm in the server space. The recent news of Ampere Computing (headed by Intel’s former president) launching their 80 co

It’s nice to see the use of 4-way SMT on Arm in the server space. The recent news of Ampere Computing (headed by Intel’s former president) launching their 80 core data-center focused Arm processor was great too, however both their processor and AWS’s Arm based Graviton processor attempt to seemingly keep things more power efficient and/or “secure” [0] by doing away with hyper-threading. While it can be argued that the security model is better without SMT as Intel’s vulnerabilities from recent years show, I have a slight hunch (Disclaimer: I have no expertise in chip design whatsoever!) that given the out-of-order execution [1] of instructions in all modern processors that there is potentially a fair bit of unused instructions capacity in each clock cycle without SMT, even for server workloads. [0] https://www.eetimes.com/startup-ampere-attacks-intels-strength/ https://www.eetimes.com/startup-ampere-attacks-intels-streng... [1] https://en.m.wikipedia.org/wiki/Out-of-order_execution https://en.m.wikipedia.org/wiki/Out-of-order_execution