SystemVerilog improves things a lot actually, but the problem is that there is (currently) no freely available, robust synthesis frontend that supports the majo

SystemVerilog improves things a lot actually, but the problem is that there is (currently) no freely available, robust synthesis frontend that supports the majority of the useful SV features (e.g. interfaces). In fact I don't think there's any robust, ~complete FOSS SystemVerilog simulators either -- though Icarus and Verilator support SV to varying degrees... So if you want to stick with FOSS tools, then you're stuck with synthesizable Verilog-2005 at best, for the moment. And standard Verilog very much sucks in a lot of ways, I would argue, synthesizable subset or not. It's an understandable choice though, in a field full of awful options. One day I'm hopeful Yosys will support most of the necessary SystemVerilog features people want for synthesis... (Then, it can also serve as an effective SystemVerilog -> Verilog translation tool, which would be very useful on its own.)