3 ms·

I've always wanted to do exactly what you just described! Can you recommend any resources to get started with FPGA design for a software dev?

magicalhippo 7y ago
I've so far been quite happy with the iCE40UP5k[1] based dev kit I got, though there are a lot of options out there[2]. The iCE40 FPGAs are a bit whimpy compared to Altera and Xilinx offerings from what I understand, but I really liked the idea of an open-source toolchain[3][4] being available. To get a taste without committing cash you could just use a simulator[5], which I imagine you'd be using a fair bit anyway as it allows you easier access to the internal state. As to actually programming, I've found the following resources useful. I started with Verilog mainly because code-gen tools like nMigen[6] generate Verilog, but for writing by hand it seems VHDL is preferred. Anyway, links, first off some exercises to get going[7]. Introduction to Verilog[8], also has a nice general overview of HDL. Details of how non-blocking vs blocking statements in Verilog works[9], quite specific but was very informative for me. There's also quite a lot of activity over at Reddit[10], and good experiences over at the EEVBlog forums[11]. As I said I just got started so no expert yet :) [1]: https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40UP5K-B-EVN/220-2134-ND/6596291 https://www.digikey.com/product-detail/en/lattice-semiconduc... [2]: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards [3]: https://symbiflow.github.io/ https://symbiflow.github.io/ [4]: https://github.com/cliffordwolf/icestorm https://github.com/cliffordwolf/icestorm [5]: http://iverilog.icarus.com/ http://iverilog.icarus.com/ [6]: https://nmigen.org https://nmigen.org [7]: https://www.fpga4fun.com/ https://www.fpga4fun.com/ [8]: https://www.chipverify.com/verilog/verilog-tutorial https://www.chipverify.com/verilog/verilog-tutorial [9]: http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBA... [10]: https://www.reddit.com/r/FPGA/ https://www.reddit.com/r/FPGA/ [11]: https://www.eevblog.com/forum/fpga/ https://www.eevblog.com/forum/fpga/
- magicalhippo 7y ago
  Forgot to mention http://www.asic-world.com/verilog/veritut.html http://www.asic-world.com/verilog/veritut.html which also has some nice explanation of HDL and hardware in general. Also it's very important to keep in mind that HDLs describe hardware, the HDL code is not executed on the hardware. Think of it as writing C++ templates.
- tails4e 7y ago
  Verilog for writing RTL is fine, especially if you use the syhthesizable subset of SystemVerilog. There used to be a bit of a religious war between VHDL and Verilog, as VHDL had some syntax that prevented certain errors, but with SV and some basic coding guidelines it's fine. While I'm sure some will still be hanging onto VHDL, I'd say most of the industry is going the SV way.
  - magicalhippo 7y ago
    Guess it might just be the bias of the forums I've been in, but most seemed to use VHDL there. Good point about SystemVerilog though.
  - aseipp 7y ago
    SystemVerilog improves things a lot actually, but the problem is that there is (currently) no freely available, robust synthesis frontend that supports the majority of the useful SV features (e.g. interfaces). In fact I don't think there's any robust, ~complete FOSS SystemVerilog simulators either -- though Icarus and Verilator support SV to varying degrees... So if you want to stick with FOSS tools, then you're stuck with synthesizable Verilog-2005 at best, for the moment. And standard Verilog very much sucks in a lot of ways, I would argue, synthesizable subset or not. It's an understandable choice though, in a field full of awful options. One day I'm hopeful Yosys will support most of the necessary SystemVerilog features people want for synthesis... (Then, it can also serve as an effective SystemVerilog -> Verilog translation tool, which would be very useful on its own.)
- ZirconiumX 7y ago
  Could you please point [6] at https://github.com/nmigen/nmigen https://github.com/nmigen/nmigen which is the new upstream after a hard fork? Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes. I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.
magicalhippo 7y ago
Oh yeah also forgot to add that once you have some hardware you'll most likely want a cheap logic analyzer that supports sigrok[1] like this[2] one. Some LEDs and a breadboard etc is useful too. [1]: https://sigrok.org/ https://sigrok.org/ [2]: https://www.aliexpress.com/item/32877931876.html https://www.aliexpress.com/item/32877931876.html (random seller link)

magicalhippo 7y ago

I've so far been quite happy with the iCE40UP5k[1] based dev kit I got, though there are a lot of options out there[2]. The iCE40 FPGAs are a bit whimpy compared to Altera and Xilinx offerings from what I understand, but I really liked the idea of an open-source toolchain[3][4] being available. To get a taste without committing cash you could just use a simulator[5], which I imagine you'd be using a fair bit anyway as it allows you easier access to the internal state. As to actually programming, I've found the following resources useful. I started with Verilog mainly because code-gen tools like nMigen[6] generate Verilog, but for writing by hand it seems VHDL is preferred. Anyway, links, first off some exercises to get going[7]. Introduction to Verilog[8], also has a nice general overview of HDL. Details of how non-blocking vs blocking statements in Verilog works[9], quite specific but was very informative for me. There's also quite a lot of activity over at Reddit[10], and good experiences over at the EEVBlog forums[11]. As I said I just got started so no expert yet :) [1]: https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40UP5K-B-EVN/220-2134-ND/6596291 https://www.digikey.com/product-detail/en/lattice-semiconduc... [2]: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards [3]: https://symbiflow.github.io/ https://symbiflow.github.io/ [4]: https://github.com/cliffordwolf/icestorm https://github.com/cliffordwolf/icestorm [5]: http://iverilog.icarus.com/ http://iverilog.icarus.com/ [6]: https://nmigen.org https://nmigen.org [7]: https://www.fpga4fun.com/ https://www.fpga4fun.com/ [8]: https://www.chipverify.com/verilog/verilog-tutorial https://www.chipverify.com/verilog/verilog-tutorial [9]: http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBA... [10]: https://www.reddit.com/r/FPGA/ https://www.reddit.com/r/FPGA/ [11]: https://www.eevblog.com/forum/fpga/ https://www.eevblog.com/forum/fpga/

magicalhippo 7y ago
Forgot to mention http://www.asic-world.com/verilog/veritut.html http://www.asic-world.com/verilog/veritut.html which also has some nice explanation of HDL and hardware in general. Also it's very important to keep in mind that HDLs describe hardware, the HDL code is not executed on the hardware. Think of it as writing C++ templates.
tails4e 7y ago
Verilog for writing RTL is fine, especially if you use the syhthesizable subset of SystemVerilog. There used to be a bit of a religious war between VHDL and Verilog, as VHDL had some syntax that prevented certain errors, but with SV and some basic coding guidelines it's fine. While I'm sure some will still be hanging onto VHDL, I'd say most of the industry is going the SV way.
- magicalhippo 7y ago
  Guess it might just be the bias of the forums I've been in, but most seemed to use VHDL there. Good point about SystemVerilog though.
- aseipp 7y ago
  SystemVerilog improves things a lot actually, but the problem is that there is (currently) no freely available, robust synthesis frontend that supports the majority of the useful SV features (e.g. interfaces). In fact I don't think there's any robust, ~complete FOSS SystemVerilog simulators either -- though Icarus and Verilator support SV to varying degrees... So if you want to stick with FOSS tools, then you're stuck with synthesizable Verilog-2005 at best, for the moment. And standard Verilog very much sucks in a lot of ways, I would argue, synthesizable subset or not. It's an understandable choice though, in a field full of awful options. One day I'm hopeful Yosys will support most of the necessary SystemVerilog features people want for synthesis... (Then, it can also serve as an effective SystemVerilog -> Verilog translation tool, which would be very useful on its own.)
ZirconiumX 7y ago
Could you please point [6] at https://github.com/nmigen/nmigen https://github.com/nmigen/nmigen which is the new upstream after a hard fork? Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes. I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.

magicalhippo 7y ago

Oh yeah also forgot to add that once you have some hardware you'll most likely want a cheap logic analyzer that supports sigrok[1] like this[2] one. Some LEDs and a breadboard etc is useful too. [1]: https://sigrok.org/ https://sigrok.org/ [2]: https://www.aliexpress.com/item/32877931876.html https://www.aliexpress.com/item/32877931876.html (random seller link)