4 ms·

The reason why mainstream DRAM interfaces are narrow and “slow” is that you need row-at-a-time access patterns to really saturate the interconnect which is some

by dfox 7y ago

The reason why mainstream DRAM interfaces are narrow and “slow” is that you need row-at-a-time access patterns to really saturate the interconnect which is something that does not happen for general purpose workloads and causing such access patterns requires large caches which by themselves solve the issue and then also physical package pins and pad structures are one of the most expensive things in semiconductor design. In end the DRAM array is bunch of analog magic and the interface works by copying the row you want into SRAM buffer on the chip which you then can access however you want. And the slowest operation in all that are the copies between SRAM row buffer and the actual DRAM array. (what I call SRAM buffer is usually called “column sense amplifiers”, but for the highlevel view it in fact is surprisingly wide array of 6T SRAM flipflops and some analog magic)

hinkley 7y ago
So how many levels of cache do we have now between the ALU and the memory cell of record??
- blattimwind 7y ago
  Physical register <-> L1 <-> Fill Buffer <-> L2 <-> L3 [<-> L4 ] <-> [bus buffer <->] memory module I wouldn't count buffer registers inside DRAM chips as a separate cache.
  - kragen 7y ago
    ↔ SSD ↔ spinning rust ↔ tarsnap or something
  - BeeOnRope 7y ago
    I wouldn't really count the fill buffer between L1 and L2 as a separate caching level, or at least if you wanted to do that you should do something similar for L2 <-> L3, L3 <-> memory controller, etc: since such buffers or queues will exist at all those places.
    - blattimwind 7y ago
      L1 Fill Buffers are somewhat special at least on Intel because a memory read can be satisfied from these before the data is written into L1.
  - dfox 7y ago
    Counting the DRAM row buffer as a separate cache layer is interesting because it has meaningful performance impact, but mainly because existence of such an thing is good counter argument to people who think that DRAM chips have RAS/CAS multiplexed address pins only to save package pins.

by dfox 7y ago

hinkley 7y ago

So how many levels of cache do we have now between the ALU and the memory cell of record??

blattimwind 7y ago
Physical register <-> L1 <-> Fill Buffer <-> L2 <-> L3 [<-> L4 ] <-> [bus buffer <->] memory module I wouldn't count buffer registers inside DRAM chips as a separate cache.
- kragen 7y ago
  ↔ SSD ↔ spinning rust ↔ tarsnap or something
- BeeOnRope 7y ago
  I wouldn't really count the fill buffer between L1 and L2 as a separate caching level, or at least if you wanted to do that you should do something similar for L2 <-> L3, L3 <-> memory controller, etc: since such buffers or queues will exist at all those places.
  - blattimwind 7y ago
    L1 Fill Buffers are somewhat special at least on Intel because a memory read can be satisfied from these before the data is written into L1.
- dfox 7y ago
  Counting the DRAM row buffer as a separate cache layer is interesting because it has meaningful performance impact, but mainly because existence of such an thing is good counter argument to people who think that DRAM chips have RAS/CAS multiplexed address pins only to save package pins.