3 ms·
The latency problem must be due to (unnecessary data) dependencies and not taking advantage of superscalar architecture. Modern CPUs support 32 or more in-fligh
by alecco 7y ago
The latency problem must be due to (unnecessary data) dependencies and not taking advantage of superscalar architecture. Modern CPUs support 32 or more in-flight memory operations.
After hiding latency, the next bottleneck would be instructions so vector scatter/gather can alleviate this problem.
- petermcneeley 7y agoIndeed. I actually think a few small modification are all that is required to significantly improve the performance of this code. I disagree with gather scatter as currently those implementations are not faster unless in the same cache line.
- BeeOnRope 7y ago32 per core? Most modern Intel only supports 10 or 12 outstanding (line) accesses per core. AMD is a bit better. Ice Lake is significantly better.
- alecco 7y agoI think it's per memory controller. Probably per socket.