5 ms·

Open Source Hardware: The Rise of RISC-V

46 points by eaguyhn 7y ago

ainar-g 7y ago
I wonder if RISC-V will be able to keep its simplicity for a long time. ARM began as a small instruction set as well, and now we have instructions like the FJCVTZS (Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero).
- moring 7y ago
  RISCV's main answer to this is to separate the instruction set into modular subsets so the baggage only has to be carried by those who need it. The core set doesn't even have multiplication.
  - tveita 7y ago
    On the other hand the instruction set extensions can be bulky. For instance the bit manipulation set at https://github.com/riscv/riscv-bitmanip https://github.com/riscv/riscv-bitmanip adds frequently used operations like conditional move and population count, but also adds things like "multiply binary matrix" and "generalized or-combine", which I'm not sure even exists in X86 or AMD64.
- VLM 7y ago
  RISC has always been a marketplace relative thing. Standard HN automobile analogy is the subcompact car class has always been the lightest car class on the road, although a 2020 subcompact car weighs about a thousand pounds more than a subcompact did when I was in high school. Think of a 1990 Geo Metro at 1500 pounds vs a 2500 pound contemporary Toyota Yaris. Its always been weird to me that an old girlfriend's Metro weighed 1000 pounds less than the Yaris I own today. The average American mass has gone from perhaps 150 pounds up to 300+ pounds over the same time frame, so weirdly enough cars are getting fat slower than humans on a percentage basis, LOL. Cars (AND RISC CPUs) don't run on corn syrup, I suppose.
  - beatgammit 7y ago
    To be fair, the average American male is 195 pounds, so you're exaggerating a little bit. But it is weird how heavy cars have gotten. I guess it's a combination of adding security features and demand for larger cars. I'm in the market for a car, and everything is just a bit larger than I remember for a given class. I dislike big cars, so finding a good fit is annoying.
    - jjuel 7y ago
      Security and luxury features. I mean the amount of tech that Yaris has compared to that old Metro is a Grand Canyon sized gorge. Add in safety features like air bags, and crash protection. The weight can increase quickly. So while the car may have weighed less you were also far less likely to enjoy driving that car, and far less likely to survive a serious crash.
- floatboth 7y ago
  ARMv8 AArch64 is actually a massive simplification, they got rid of all the crap that accumulated in 32-bit arch, it's very clean and nice. The presence of some very specific (but immensely popular) float rounding instructions does not make an ISA complex.
- magicalhippo 7y ago
  I'm no expert, but isn't the "reduced" in RISC about what the instructions do (and don't do) rather than the number of instructions in an ISA? FJCVTZS[1] seems pretty specialized, but it also seems rather simple. It converts the value in one register and puts the result in another register. Compare that with say MOVSB[2] from X86, which reads from memory, writes to memory and updates two registers. [1]: https://developer.arm.com/docs/100069/0607/a64-floating-point-instructions/fjcvtzs https://developer.arm.com/docs/100069/0607/a64-floating-poin... [2]: https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:movsq https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:mov...
  - sifar 7y ago
    In theory, RISC meant smaller number of simpler generic instructions (reg<->reg, mem<->reg) which could be re-used to build complex functionality. However in practice one always needs specific operations for performance reasons. Having more and more specialized operations not only adds extra HW for rarely used ops, it also increases the program code size and also compiler complexity.
melling 7y ago
“ In China, for example, the foundation has 30 members, and more than 200 people participating in local RISC-V associations.” The second largest economy is going to run with this. After the trade war, they’ll reduce exposure to US restrictions.
- rwmj 7y ago
  Been happening for a while. There are big fabless companies in China adopting RISC-V. It's a combination of the trade war and the opportunity to save money on ARM licenses.
azhenley 7y ago
At the university that I work at, some of our operating systems courses have already adopted RISC-V. So hopefully it is around to stay. Some of the material is publicly available in an online book/blog form written by our lecturer: http://osblog.stephenmarz.com/index.html http://osblog.stephenmarz.com/index.html
VLM 7y ago
There's a lot of "what" in the article, not so much "why" or "history". Every decade or so, someone tries an open, current technology and specs CPU. Plenty of free FOSS or FOSS-like z80 or 6502 cores out there, not so many cutting edge designs. The key differentiator with RISC-V is its pretty near cutting edge compared to every other free core out there. There are tons of cores out there for FPGAs but usually they are not cutting edge powerful (although close...) and they always have interesting and expensive licensing for non-trivial use. RISC-V should, once community support and toolchains catch up, eat every licensing dollar currently being spent on Xylinx Microblaze or Intel/Altera NIOS-II. So there's money laying around interested in RISC-V. Or a more negative way of looking at it is there's a lot of money thats interested in not seeing RISC-V succeed. Around the turn of the century, the same idea was OpenSPARC. Around last decade, the same idea was OpenPOWER. Now, its RISC-V and ... maybe its going to be a winner? Its about time.
- floatboth 7y ago
  POWER actually became a royalty-free ISA very very recently, way after the initial RISC-V hype. When the term OpenPOWER was introduced, it was mostly about the ecosystem – open standards for boot/ABI/etc, openness to board makers (hello Raptor), open firmware and so on. BTW: RISC-V being a royalty-free ISA does not mean every implementation is gonna be open source. Though it seems like SiFive's implementation is.
- zozbot234 7y ago
  > The key differentiator with RISC-V is its pretty near cutting edge compared to every other free core out there. I thought it was an express goal of RISC-V to not depend on cutting-edge features in the ISA, in order to avoid the IP issues that constrain most other architectures, and also to keep basic implementations simple enough for e.g. educational use. Although RISC-V also puts quite a bit of emphasis on being open to extensibility, which requires some extra attention in e.g. making efficient use of the ISA encoding space.
- leggomylibro 7y ago
  It's also less vulnerable to global trade conflicts. A royalty-free license means that you don't have to depend on a company like ARM for your CPU design. For example, if you're a Chinese manufacturer who relies on STM32 chips with their ARM Cortex-M cores and you're worried about the winds of global trade, what do you do? It looks like you make a new line of RISC-V chips with the same memory and peripheral layout. Problem solved: https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ https://www.gigadevice.com/products/microcontrollers/gd32/ri... And as a consequence, civilians who live in heavily-sanctioned places like Iran can also learn about modern embedded computing more easily on a budget. The economic incentives to produce actual hardware brings the ISA out of FPGA-land, which can improve equality of access and opportunity around the world. It might also help that the ISA is designed in a modular way so that it can be suitable for everything from small microcontrollers to large-scale application processors.
daffy 7y ago
When will it be possible for a semi-technical person to buy or build a RISC-V Linux desptop computer?
- rwmj 7y ago
  Not for many years. This isn't really a use case that anyone is interested in, and there's next to no money in it so no company will bother. If it happens at all it'll be like ARM and x86 - basically a side-effect of chips becoming cheap because they are used in other contexts (phones/tablets for ARM, Windows machines for x86). RISC-V will first be important in embedded applications simply as a way to avoid paying ARM royalties. Then in servers for people who want an easy way to add instruction extensions without having to beg Intel.
- rjsw 7y ago
  You could buy a HiFive Unleashed board with the expansion board then add a PCI graphics card. You would also need a PCI USB host card for keyboard and mouse. This isn't cheap though.
ColanR 7y ago
So are RISC-V chips already available? Or is it that the chips available are all low power things. I'm curious how much effort is left, before it's possible to build an open source PCB that those who wanted to could send off to be printed and populated, which could serve as some kind of MVP motherboard.
- deleted 7y ago
  [deleted]
- leggomylibro 7y ago
  GD32VF103 chips are similar to STM32F103s and you can get boards with them for ~$5: https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF103CBT6-Development-Board-p-4205.html https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF... Kendryte K210 modules are a bit more expensive, but they include an "AI coprocessor" which looks like a sort of SIMD accelerator. They come in creepy "camera+wifi" form factors for all of your dystopian facial recognition needs: https://www.seeedstudio.com/Sipeed-M1w-dock-suit-M1w-dock-2-4-inch-LCD-OV2640-K210-Dev-Board-1st-RV64-AI-board-for-Edge-Computing-p-3207.html https://www.seeedstudio.com/Sipeed-M1w-dock-suit-M1w-dock-2-... And if you're willing to spend a bit more, SiFive also sells "Freedom" boards which are more like SBCs than microcontrollers: https://www.sifive.com/boards https://www.sifive.com/boards
  - ColanR 7y ago
    Very cool. It looks like there is a board like what I was imagining, 1.5GHz quad core + 8GB DDR4 RAM, but it's not for sale anymore. Limited run crowdfunding. The design files and schematics are available, though, so I guess it's possible to get the boards built. Thanks for the links.
jhallenworld 7y ago
RISC-V is interesting for Lattice ECP5 specifically. I'm working on a project now where I'm using it (I will make a blog or videos about it at some point): - ECP5 is the lowest cost medium size FPGA. Usually I would say that using a soft core is a waste of money vs. an external microcontroller unless you need to save space, but the cost of the added gates (say the next larger FPGA size than what you would need for a design without the soft core) is less than the cost of a microcontroller for the case where you are using ECP5 and you need video (a non-video micro is still cheaper). - Mico32 is Lattice's soft core solution. You can argue about its quality, but the very stupid reason that I prefer RISC-V is that the Mico32 tool chain does not work in Ubuntu (or at least not without a lot of work- it is supposed to work in RedHat). A lot of other people complain about Mico32 because it will not run Linux, but this is not so much of an issue for my design. - PicoRV32 is designed for high clock speed. This is probably not good for its own performance (multiple cycles per instruction), but it does mean that the RISC-V core is not the limiting factor for the rest of your FPGA design. https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 - The barrier to entry is low (as long as you already know GCC linker scripts). The problem with NIOS-II and especially Xilinx Microblaze is that the their tools are not simple. There is a payoff for learning their tools, in that a lot of vendor cores become available. But if you don't need the vendor cores, then the non-existent toolchain (there is no system building to learn) for RISC-V is better. An example of this is the following project trellis (a cool open source FPGA toolchain, but that's another story) example design: https://github.com/SymbiFlow/prjtrellis/tree/master/examples/picorv32_versa5g https://github.com/SymbiFlow/prjtrellis/tree/master/examples...
ncmncm 7y ago
My main disappointment with RISC-V is that the optional swathes of the instuction set are all-or-nothing, and they are each huge. E.g., I don't get popcount without a hell of a lot else (none of which is actually out, yet), similarly for others. Maybe this wouldn't matter if they almost always have everything, but that doesn't seem to be the case; certainly B are thin on the ground, for known reasons. The second disappointment is that they flubbed the once-in-a-generation opportunity to represent the boolean true value as all-1s, which would make it also useful as a mask. Third is that the comparison and conditional-branch instructions are merged, impoverishing the sets of comparisons and branches. (E.g., comparisons could set an output register to zero or all-ones, and branches could then depend on a register.) You might consider these pretty small disappointments, but I feel them no less keenly for that.

46 points by eaguyhn 7y ago

I wonder if RISC-V will be able to keep its simplicity for a long time. ARM began as a small instruction set as well, and now we have instructions like the FJCVTZS (Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero).

moring 7y ago
RISCV's main answer to this is to separate the instruction set into modular subsets so the baggage only has to be carried by those who need it. The core set doesn't even have multiplication.
- tveita 7y ago
  On the other hand the instruction set extensions can be bulky. For instance the bit manipulation set at https://github.com/riscv/riscv-bitmanip https://github.com/riscv/riscv-bitmanip adds frequently used operations like conditional move and population count, but also adds things like "multiply binary matrix" and "generalized or-combine", which I'm not sure even exists in X86 or AMD64.
VLM 7y ago
RISC has always been a marketplace relative thing. Standard HN automobile analogy is the subcompact car class has always been the lightest car class on the road, although a 2020 subcompact car weighs about a thousand pounds more than a subcompact did when I was in high school. Think of a 1990 Geo Metro at 1500 pounds vs a 2500 pound contemporary Toyota Yaris. Its always been weird to me that an old girlfriend's Metro weighed 1000 pounds less than the Yaris I own today. The average American mass has gone from perhaps 150 pounds up to 300+ pounds over the same time frame, so weirdly enough cars are getting fat slower than humans on a percentage basis, LOL. Cars (AND RISC CPUs) don't run on corn syrup, I suppose.
- beatgammit 7y ago
  To be fair, the average American male is 195 pounds, so you're exaggerating a little bit. But it is weird how heavy cars have gotten. I guess it's a combination of adding security features and demand for larger cars. I'm in the market for a car, and everything is just a bit larger than I remember for a given class. I dislike big cars, so finding a good fit is annoying.
  - jjuel 7y ago
    Security and luxury features. I mean the amount of tech that Yaris has compared to that old Metro is a Grand Canyon sized gorge. Add in safety features like air bags, and crash protection. The weight can increase quickly. So while the car may have weighed less you were also far less likely to enjoy driving that car, and far less likely to survive a serious crash.
floatboth 7y ago
ARMv8 AArch64 is actually a massive simplification, they got rid of all the crap that accumulated in 32-bit arch, it's very clean and nice. The presence of some very specific (but immensely popular) float rounding instructions does not make an ISA complex.
magicalhippo 7y ago
I'm no expert, but isn't the "reduced" in RISC about what the instructions do (and don't do) rather than the number of instructions in an ISA? FJCVTZS[1] seems pretty specialized, but it also seems rather simple. It converts the value in one register and puts the result in another register. Compare that with say MOVSB[2] from X86, which reads from memory, writes to memory and updates two registers. [1]: https://developer.arm.com/docs/100069/0607/a64-floating-point-instructions/fjcvtzs https://developer.arm.com/docs/100069/0607/a64-floating-poin... [2]: https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:movsq https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:mov...
- sifar 7y ago
  In theory, RISC meant smaller number of simpler generic instructions (reg<->reg, mem<->reg) which could be re-used to build complex functionality. However in practice one always needs specific operations for performance reasons. Having more and more specialized operations not only adds extra HW for rarely used ops, it also increases the program code size and also compiler complexity.

melling 7y ago

“ In China, for example, the foundation has 30 members, and more than 200 people participating in local RISC-V associations.” The second largest economy is going to run with this. After the trade war, they’ll reduce exposure to US restrictions.

rwmj 7y ago
Been happening for a while. There are big fabless companies in China adopting RISC-V. It's a combination of the trade war and the opportunity to save money on ARM licenses.

azhenley 7y ago

At the university that I work at, some of our operating systems courses have already adopted RISC-V. So hopefully it is around to stay. Some of the material is publicly available in an online book/blog form written by our lecturer: http://osblog.stephenmarz.com/index.html http://osblog.stephenmarz.com/index.html

VLM 7y ago

There's a lot of "what" in the article, not so much "why" or "history". Every decade or so, someone tries an open, current technology and specs CPU. Plenty of free FOSS or FOSS-like z80 or 6502 cores out there, not so many cutting edge designs. The key differentiator with RISC-V is its pretty near cutting edge compared to every other free core out there. There are tons of cores out there for FPGAs but usually they are not cutting edge powerful (although close...) and they always have interesting and expensive licensing for non-trivial use. RISC-V should, once community support and toolchains catch up, eat every licensing dollar currently being spent on Xylinx Microblaze or Intel/Altera NIOS-II. So there's money laying around interested in RISC-V. Or a more negative way of looking at it is there's a lot of money thats interested in not seeing RISC-V succeed. Around the turn of the century, the same idea was OpenSPARC. Around last decade, the same idea was OpenPOWER. Now, its RISC-V and ... maybe its going to be a winner? Its about time.

floatboth 7y ago
POWER actually became a royalty-free ISA very very recently, way after the initial RISC-V hype. When the term OpenPOWER was introduced, it was mostly about the ecosystem – open standards for boot/ABI/etc, openness to board makers (hello Raptor), open firmware and so on. BTW: RISC-V being a royalty-free ISA does not mean every implementation is gonna be open source. Though it seems like SiFive's implementation is.
zozbot234 7y ago
> The key differentiator with RISC-V is its pretty near cutting edge compared to every other free core out there. I thought it was an express goal of RISC-V to not depend on cutting-edge features in the ISA, in order to avoid the IP issues that constrain most other architectures, and also to keep basic implementations simple enough for e.g. educational use. Although RISC-V also puts quite a bit of emphasis on being open to extensibility, which requires some extra attention in e.g. making efficient use of the ISA encoding space.
leggomylibro 7y ago
It's also less vulnerable to global trade conflicts. A royalty-free license means that you don't have to depend on a company like ARM for your CPU design. For example, if you're a Chinese manufacturer who relies on STM32 chips with their ARM Cortex-M cores and you're worried about the winds of global trade, what do you do? It looks like you make a new line of RISC-V chips with the same memory and peripheral layout. Problem solved: https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ https://www.gigadevice.com/products/microcontrollers/gd32/ri... And as a consequence, civilians who live in heavily-sanctioned places like Iran can also learn about modern embedded computing more easily on a budget. The economic incentives to produce actual hardware brings the ISA out of FPGA-land, which can improve equality of access and opportunity around the world. It might also help that the ISA is designed in a modular way so that it can be suitable for everything from small microcontrollers to large-scale application processors.

daffy 7y ago

When will it be possible for a semi-technical person to buy or build a RISC-V Linux desptop computer?

rwmj 7y ago
Not for many years. This isn't really a use case that anyone is interested in, and there's next to no money in it so no company will bother. If it happens at all it'll be like ARM and x86 - basically a side-effect of chips becoming cheap because they are used in other contexts (phones/tablets for ARM, Windows machines for x86). RISC-V will first be important in embedded applications simply as a way to avoid paying ARM royalties. Then in servers for people who want an easy way to add instruction extensions without having to beg Intel.
rjsw 7y ago
You could buy a HiFive Unleashed board with the expansion board then add a PCI graphics card. You would also need a PCI USB host card for keyboard and mouse. This isn't cheap though.

ColanR 7y ago

So are RISC-V chips already available? Or is it that the chips available are all low power things. I'm curious how much effort is left, before it's possible to build an open source PCB that those who wanted to could send off to be printed and populated, which could serve as some kind of MVP motherboard.

deleted 7y ago
[deleted]
leggomylibro 7y ago
GD32VF103 chips are similar to STM32F103s and you can get boards with them for ~$5: https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF103CBT6-Development-Board-p-4205.html https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF... Kendryte K210 modules are a bit more expensive, but they include an "AI coprocessor" which looks like a sort of SIMD accelerator. They come in creepy "camera+wifi" form factors for all of your dystopian facial recognition needs: https://www.seeedstudio.com/Sipeed-M1w-dock-suit-M1w-dock-2-4-inch-LCD-OV2640-K210-Dev-Board-1st-RV64-AI-board-for-Edge-Computing-p-3207.html https://www.seeedstudio.com/Sipeed-M1w-dock-suit-M1w-dock-2-... And if you're willing to spend a bit more, SiFive also sells "Freedom" boards which are more like SBCs than microcontrollers: https://www.sifive.com/boards https://www.sifive.com/boards
- ColanR 7y ago
  Very cool. It looks like there is a board like what I was imagining, 1.5GHz quad core + 8GB DDR4 RAM, but it's not for sale anymore. Limited run crowdfunding. The design files and schematics are available, though, so I guess it's possible to get the boards built. Thanks for the links.

jhallenworld 7y ago

RISC-V is interesting for Lattice ECP5 specifically. I'm working on a project now where I'm using it (I will make a blog or videos about it at some point): - ECP5 is the lowest cost medium size FPGA. Usually I would say that using a soft core is a waste of money vs. an external microcontroller unless you need to save space, but the cost of the added gates (say the next larger FPGA size than what you would need for a design without the soft core) is less than the cost of a microcontroller for the case where you are using ECP5 and you need video (a non-video micro is still cheaper). - Mico32 is Lattice's soft core solution. You can argue about its quality, but the very stupid reason that I prefer RISC-V is that the Mico32 tool chain does not work in Ubuntu (or at least not without a lot of work- it is supposed to work in RedHat). A lot of other people complain about Mico32 because it will not run Linux, but this is not so much of an issue for my design. - PicoRV32 is designed for high clock speed. This is probably not good for its own performance (multiple cycles per instruction), but it does mean that the RISC-V core is not the limiting factor for the rest of your FPGA design. https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 - The barrier to entry is low (as long as you already know GCC linker scripts). The problem with NIOS-II and especially Xilinx Microblaze is that the their tools are not simple. There is a payoff for learning their tools, in that a lot of vendor cores become available. But if you don't need the vendor cores, then the non-existent toolchain (there is no system building to learn) for RISC-V is better. An example of this is the following project trellis (a cool open source FPGA toolchain, but that's another story) example design: https://github.com/SymbiFlow/prjtrellis/tree/master/examples/picorv32_versa5g https://github.com/SymbiFlow/prjtrellis/tree/master/examples...

ncmncm 7y ago

My main disappointment with RISC-V is that the optional swathes of the instuction set are all-or-nothing, and they are each huge. E.g., I don't get popcount without a hell of a lot else (none of which is actually out, yet), similarly for others. Maybe this wouldn't matter if they almost always have everything, but that doesn't seem to be the case; certainly B are thin on the ground, for known reasons. The second disappointment is that they flubbed the once-in-a-generation opportunity to represent the boolean true value as all-1s, which would make it also useful as a mask. Third is that the comparison and conditional-branch instructions are merged, impoverishing the sets of comparisons and branches. (E.g., comparisons could set an output register to zero or all-ones, and branches could then depend on a register.) You might consider these pretty small disappointments, but I feel them no less keenly for that.