8 ms·
As long as we're wishing... These kinds of projects always take you up to where CPUs were in the early 1950s on Large Systems or the 1970s in the home computin
by msla 7y ago
As long as we're wishing...
These kinds of projects always take you up to where CPUs were in the early 1950s on Large Systems or the 1970s in the home computing world: Single-issue processors with no memory protection or privilege levels. They work, in that you can write useful software for those systems, but taken as a way to explain how CPUs work in a holistic fashion they fall well short. They simply aren't complex enough to explain why Meltdown happens, for example: Since there is no concept of privilege to begin with, you can't use them to explain privilege level violations. More prosaically, you can't explain a "cold cache" when the processor doesn't have a cache which can be cold.
This is demoralizing for the poor sods who think they're going to learn how CPUs work and end up with a CPU design which is decades out of date and no way to extend it to even a thirty-year-old design. "You can't get there from here" is the bane of tutorials which explain the basics and then stop.
- jacobush 7y agoStill, understanding any general purpose CPU gets you most of the way. Virtual memory and memory protection isn't terribly far off, could be implemented using paging. A very simple feature complete system could be made. A very basic model, yet working. A union between theory and practice- Heartbleed is because of memory and cache shenanigans. More like how things can get wrong if you optimize too hard. While important, it feels like another line of thinking.
- tyingq 7y agoThat seems a bit harsh. You have to start somewhere, and this teaches basic stuff like an ALU, Clock, Accumulator, etc. Some homebrew CPUs have memory bank switching. Moving to an FPGA based CPU might be the next step. There are soft CPUs with cache, MMU, etc. (https://github.com/SpinalHDL/VexRiscv https://github.com/SpinalHDL/VexRiscv for example)
- namibj 7y agoThe picorv32 project offers a RISC-V core that only lacks MMU/privileges, but the memory interface should make a cache quite easy to add. The gate count won't be that bad, considering it's only ~700 LUTs in Xilinx 7-series FPGA. I think it'd fit in <10k gates, not counting the registers.
- msla 7y agoI don't intend to be harsh, but I am disappointed that there's apparently no ramp-up from the basics to a modern CPU design, that you get taken to some point where everything works but there's no path to stuff like out-of-order execution.
- fizixer 7y agoSo as I understand: - H&P does a very good job of giving updating arch knowledge, but it's mainly "theoretical" - In order to build/simulate modern arch features, a lot of work needs to be done. So we have simulators like gem5. Do you think what's seriously lacking is, for some expert to sit down with H&P and gem5, implement a ton of modern features, analyze them, and write a big textbook about it along the lines of 'Practical Computer Architecture'?
- msla 7y ago> Do you think what's seriously lacking is, for some expert to sit down with H&P and gem5, implement a ton of modern features, analyze them, and write a big textbook about it along the lines of 'Practical Computer Architecture'? That would certainly help. Another good step in the right direction would simply be taking a processor with a good mix of modern features and giving a guided tour. Everything is done by something, so show all of those somethings and how they're put together, and how they all fit together into a complete design.
- mrguyorama 7y agoConsider researching different CPU architecture college classes. My friend took one that involved building a CPU with functions like out of order execution etc, while mine did not