Amortized against L2 cache, MMU, SIMD floating-point units, and Out-of-Order engines, 64-bit integer ALUs and data paths are not a big change. Many or all of t

Amortized against L2 cache, MMU, SIMD floating-point units, and Out-of-Order engines, 64-bit integer ALUs and data paths are not a big change. Many or all of those features are not present in the published design wins for RISC-V.