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> Yann Herklotz‘s paper on “Finding and Understanding Bugs in FPGA Synthesis Tools” described his efforts to find bugs in tools like Quartus, Vivado, and Yosys;
by ohazi 7y ago
> Yann Herklotz‘s paper on “Finding and Understanding Bugs in FPGA Synthesis Tools” described his efforts to find bugs in tools like Quartus, Vivado, and Yosys; his presentation was greeted with an amusing mixture of alarm and pride from the developers of these tools, depending on the respective number of bugs he found in each!
Linked paper has a summary of the bugs found:
https://yannherklotz.com/docs/verismith/verismith_paper.pdf https://yannherklotz.com/docs/verismith/verismith_paper.pdf
Also from the paper:
> All the bugs mentioned were reported and confirmed by the tool maintainers and vendors. Most of the Yosys bugs were fixed within the day, whereas Xilinx confirmed the bug and intend to “fix this issue in future releases”.
And this is why open source tools are better in the long run.
- jeremysalwen 7y agoI remember running a fuzzer on yosys and reporting several bugs that popped up years ago, and Clifford was very prompt and responsive fixing them.
- swiley 7y agoAs a hobbyist I have to say: Yosis is just so much more pleasant to use than the commercial tools, even if it were horribly buggy I think I would prefer it.
- tverbeure 7y agoIs that an apples to apples experience comparison? I use Quartus primarily in a Makefile, just the way I use Yosys and Nextpnr in a Makefile. There really isn’t a whole lot of first order difference. But with Quartus, you get better language support, vastly better timing constraints, and excellent debugging tools. I recently did the test compiling an identical design from RTL to bitstream for both Yosys/Nextpnr and Quartus, and the speed to completion was very close (though the fill percentage for the Lattice part was much higher.) Quartus gets a lot of criticism for its GUI/editor, but that’s a product category in which Yosys doesn’t even play.
- fit2rule 7y agoYosys seems to me to be quite ripe for a GUI add-on. Its cleanliness and elegance befit the KISS ideology of an OpenSCAD-style IDE.
- tverbeure 7y agoI honestly don’t see why or how? It’s a synthesis tool. RTL goes in, logic elements go out. It doesn’t need a GUI just like Synopsys DC doesn’t need a GUI. If an IDE for RTL design is your thing, you use a generic tool that may or may not have bindings to invoke Yosys from some menu option, just like Eclipse can be used to call GCC.
- Rochus 7y agoSee https://github.com/rochus-keller/VerilogCreator/blob/master/README.md https://github.com/rochus-keller/VerilogCreator/blob/master/... for a compatible IDE.