Moreover, the 3 operand case is the slow path for LEA and then there's only 1 execution port for it on Skylake, Port 1, vs 2 ports for fast LEAs. The slow path

Moreover, the 3 operand case is the slow path for LEA and then there's only 1 execution port for it on Skylake, Port 1, vs 2 ports for fast LEAs. The slow path is 3 cycles vs fast path's 1 cycle: Intel even recommends: Assembly/Compiler Coding Rule 30. (ML impact, L generality) If an LEA instruction using the scaled index is on the critical path, a sequence with ADDs may be better. As to the article, partial register stalls aren't that bad on modern CPUs, not 5-6 cycles. And CFLAG bits get renamed. I think the article gets at that. Basically, anything which sticks out in a real benchmark gets hammered down and optimized by Intel.